Abstract: A transmission of feedback information from a secondary to a primary node occurs in a plurality of N logical time durations. The secondary node receives an allocation of resources comprising a plurality of resource elements on an uplink shared data channel. The secondary node generates feedback information in response to transmissions from the primary node and normally transmits feedback information to the primary node on a control channel. On occasion, the secondary node receives a trigger from the primary node. In response to the trigger, the secondary node transmits the feedback information using a subset of the allocated resource elements on the uplink shared data channel.

Abstract: An integrated circuit with standard cells with top and bottom metal-1 and metal-2 power rails and with lateral standard cell borders that lie between an outermost vertical dummy poly lead from one standard cell and an adjacent standard cell. A DPT compatible standard cell design rule set. A method of forming an integrated circuit with standard cells constructed using a DPT compatible standard cell design rule set. A method of forming DPT compatible standard cells.

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.

Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.

Abstract: An integrated circuit with a high precision MIM capacitor and a high precision resistor with via etch stop landing pads on the resistor heads that are formed with the capacitor bottom plate material. A process of forming an integrated circuit with a high precision MIM capacitor and a high precision resistor where via etch stop landing pads over the resistor heads are formed using the same layer that is used to form the capacitor bottom plate.

Abstract: An electronic circuit (300) includes a signal processing circuit (310) including first and second signal processing blocks (310.1, 310.3) coupled in cascade, a memory circuit (320) coupled to and adjustable between the first and second signal processing blocks (310.1, 310.3), the memory circuit (320) having memory spaces, the memory circuit (320) configurable to establish a trade-off of the memory spaces between the first and second signal processing blocks (310.1, 310.3), and a configuring circuit (330) operable to configure the trade-off of the memory spaces of the memory circuit (320).

Abstract: A mobile system for analyzing ECG data includes an analog front end module coupled to a mobile consumer device. The analog front end module is configured to collect ECG data from one or more leads and is operable to convert the analog ECG data to digital ECG data. The mobile consumer device is coupled to receive the digital ECG data, and is configured to perform QRS detection using a filter whose cutoff frequency is adapted to noise level in real time. The ECG signal is amplified non-linearly and three windowed threshold signals (D, E, J) are derived. The cutoff frequency for the QRS detection is dynamically selected as a function of the threshold signals. A sample in the amplified signal is identified to be a heart beat point only when the sample value is equal to the first threshold signal and greater than the filtered threshold signal.

Abstract: A filter is implemented as cascaded stages, and in at least one stage all resistances are implemented as double-sampled switched-capacitor circuits. In a variation, at least one resistance is implemented as a double-sampled switched-capacitor T-network. In a variation, in an integrator stage, a resistance is implemented as a transconductance, and the cutoff frequency of the integrator stage scales with a switching frequency of a DC-DC voltage converter.

Abstract: Ferroelectric capacitor structures for integrated decoupling capacitors and the like. The ferroelectric capacitor structure includes two or more ferroelectric capacitors connected in series with one another between voltage nodes. The series connection of the ferroelectric capacitors reduces the applied voltage across each, enabling the use of rough ferroelectric dielectric material, such as PZT deposited by MOCVD. Matched construction of the series-connected capacitors, as well as uniform polarity of the applied voltage across each, is beneficial in reducing the maximum voltage across any one of the capacitors, reducing the vulnerability to dielectric breakdown.

Abstract: An integrated circuit with a LV transistor and a high performance asymmetric transistor. A power amplifier integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming an integrated circuit with a core transistor and a high performance asymmetric transistor. A method of forming a power amplifier integrated circuit with an nmos core transistor and an nmos high performance asymmetric transistor, a resistor, and an inductor.

Abstract: A method of programming a memory array having plural subarrays is disclosed. (FIG. 3). The method includes determining a minimum operating voltage (Vmin) for each subarray of the plural subarrays (306). A first voltage is applied to each subarray having a minimum operating voltage greater than a predetermined voltage (420, 422, 424). A second voltage is applied to each subarray having a minimum operating voltage less than the predetermined voltage (308 and 426, 428).

Abstract: Embodiments of the invention provide methods for key fob to control unit verification, retention, and revocation. After an initial pairing between a key fob and a control unit, the devices share a secret operation key (OpKey). For verification, the key fob sends the 8 lowest-order bits of a 128-bit counter and some bits of an AES-128, OpKey encrypted value of the counter to the control unit. For key revocation and retention, the control unit is prompted to enter an OpKey retention and revocation mode. Subsequently, each of the remaining or new key fobs is prompted by the user to send a verification message to the control unit. When the control unit is prompted to exit the OpKey retention and revocation mode, it retains the OpKeys of only the key fobs that sent a valid verification message immediately before entering and exiting the OpKey retention and revocation mode.

Abstract: A mobile device, such as a smart phone, is provided with a camera and a projector. A user may select a still image or a video sequence and project it onto a viewing surface using the mobile device. Once the viewer selects a preferred perspective view frame, the image frame may be pinned to the viewing surface. After that, the viewer may move the projector to different positions while holding the projector, or sit the projector on a table and the viewed image will be maintained in the same perspective view frame as the initial selected view.

Abstract: A Global Navigation Satellite System (GNSS) receiver determines a measurement error covariance from a reference position and a set of measured pseudoranges from a set of GNSS satellites. The position and velocity solution is determined from the measurement error covariance and the set of measured pseudoranges. The measurement error covariance is determined as function of the difference between a reference pseudorange and measured pseudorange. The reference pseudorange is computed from the reference position to a satellite. The measurement error covariance is determined as function of the difference only if the measured pseudorange is greater than the reference pseudorange. The GNSS receiver also determines measurement error covariance as function of one or more of correlation peak shape, difference, the correlation peak shape, a received signal to noise ratio and a tracking loop error.

Abstract: An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric layer exposing, and not overlapping, the bottom plate, a capacitor dielectric layer covering sidewalls and a bottom of the capacitor opening, a top plate covering the capacitor dielectric layer in the capacitor opening, and a capacitor planarizing dielectric layer covering the capacitor top plate in the capacitor opening. A top surface of the capacitor planarizing dielectric layer and a top edge of the capacitor top plate are substantially coplanar. The top plate does not extend laterally beyond the capacitor opening. A method of forming the integrated circuit the high precision capacitor is also disclosed.

Abstract: A peak-to-average ratio (PAR) of a signal is reduced by clipping the signal at a threshold level and replacing desired frequency tones of the clipped signal with set of frequency tones of the signal. In one embodiment, the PAR of a signal is reduced by adding a peak cancellation signal to the received signal. The peak cancellation signal is generated by clipping the received signal at a threshold level and generating a difference signal by subtracting the received signal from the clipped signal. The peak cancellation signal thus generated is scaled by a scaling factor and added to the received signal to reduce the PAR of the received signal. The scaling factor is adjusted to maintain the desired quality of the received signal. In one embodiment, the PAR of an orthogonal frequency division multiplexed (OFDM) signal may be reduced.

Abstract: A scannable storage circuit includes a scan enable input, a storage element having a Node coupled to a data output buffer for driving a data output terminal. The data output buffer includes an inverter; a transmission gate having a first MOS transistor and a second MOS transistor with sources and drains coupled to each other, drains coupled to an output of the inverter and sources coupled to the data output terminal and gates coupled to the scan enable input and an inverted scan enable input. A third MOS transistor and a fourth MOS transistor is coupled to the sources of the first and second MOS transistors, the third MOS transistor and fourth MOS transistor are configured to pull up or pull down the data output terminal in response to a first control signal and a second control signal respectively. A scan output is generated from the output of the inverter.

Abstract: A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.

Abstract: A semiconductor device contains a vertical MOS transistor with instances of a vertical RESURF trench on opposite sides of a vertical drift region. The vertical RESURF trench contains a dielectric trench liner on sidewalls, and a lower field plate and an upper field plate above the lower field plate. The dielectric trench liner between the lower field plate and the vertical drift region is thicker than between the upper field plate and the vertical drift region. A gate is disposed over the vertical drift region and is separate from the upper field plate. The upper field plate and the lower field plate are electrically coupled to a source electrode of the vertical MOS transistor.