Abstract: A semiconductor device containing a GaN FET has n-type doping in at least one III-N semiconductor layer of a low-defect layer and an electrical isolation layer below a barrier layer. A sheet charge carrier density of the n-type doping is 1 percent to 200 percent of a sheet charge carrier density of the two-dimensional electron gas.

Abstract: An error monitor receives a first list of selected system events with each selected system event having an associated range. The occurrence of each selected system event is counted over a selected time period. An error indication is provided based on a comparison of each of the counts of the occurrence of each selected system event over the selected time period with the associated range. Operational profiles are used to store lists of selected system events with each selected system event having an associated range for each operational profile.

Abstract: A method of protecting software for embedded applications against unauthorized access. Software to be protected is loaded into a protected memory area. Access to the protected memory area is controlled by sentinel logic circuitry. The sentinel logic circuitry allows access to the protected memory area from only either within the protected memory area or from outside of the protected memory area but through a dedicated memory location within the protected memory area. The dedicated memory location then points to protected address locations within the protected memory area.

Abstract: A method for assembling die packages includes attaching contacts on a first side of a plurality of first die to substrate pads on a top surface of a composite carrier. The composite carrier includes a package substrate including at least one embedded metal layer having its bottom surface secured to a semiconductor wafer. The composite carrier minimizes effects of the CTE mismatch between the die and the package substrate during assembly reduces warpage of the die. After the attaching, the semiconductor wafer is removed from the package substrate. Electrically conductive connectors are attached to the bottom surface of the package substrate, and the package substrate is sawed to form a plurality of singulated die packages.

Abstract: A method for fabricating an integrated circuit (IC) includes initial oxidizing of a semiconductor surface of a substrate. The substrate is heated after the initial oxidizing using a plurality of furnace processing steps which each include a peak processing temperature between 800° C. and 1300° C. The furnace processing steps include at least one accelerated processing step having an accelerated ramp portion in a temperature range between 800° C. and 1250° C. providing an accelerated ramp-up rate and/or an |accelerated ramp-down rate| of at least (?) 5.5° C./min.

Abstract: An method for driving a motor is provided. A plurality of pulse width modulation (PWM) signals are generated from a commanded voltage signal and a commanded angle signal, and these PWM signal are used to drive a motor (which has a plurality of phases). Currents through the phases of the motor are measured, and a Park transformation is performed on the measured currents to determine a projection current measurement. Based at least in part on the projection current measurement, the adjusting the commanded voltage signal and the commanded angle signal can be adjusted.

Abstract: A tool for performing a functional safety analysis of an integrated circuit device tailored to a customer's specific application and implementation of the device. Information regarding a user's specific implementation of a given integrated circuit device is provided by the customer as input to the safety analysis tool. The tool then automatedly performs a functional safety analysis based on the information regarding the user's specific implementation of the integrated circuit device. In one embodiment, the customer specifies specific functional modules of the integrated circuit device, and the tool performs a functional safety analysis of the integrated circuit device that considers the functional modules selected by the user.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: A system and method for detecting a USB cable-type. A USB PD device configured at a near end of a USB cable is configured to (i) receive and process a signal from a device at a far end of the USB cable to determine a power rating of the USB cable and (ii) adjustably establish power delivered by the first device to the USB cable as a function of the determined USB cable power rating.

Abstract: An apparatus is provided. A comparison circuit is configured to receive an analog signal. A reference circuit is coupled to the comparison circuit and is configured to provide a plurality of reference signals to the comparison circuit. A conversion circuit is coupled to the comparison circuit and is configured to detect a change in the output of the comparison circuit. A time-to-digital converter (TDC) is coupled to the comparison circuit. A timer is coupled to the comparison circuit. A rate control circuit is coupled to the conversion circuit. An output circuit is coupled to the rate control circuit and the TDC, where the output circuit is configured to output at least one of a synchronous digital representation of the analog signal and an asynchronous digital representation of the analog signal.

Abstract: A method of fabricating a photodiode array having different photodiode structures includes providing a semiconductor substrate having first and second diode areas including a bottom substrate portion doped with a first doping type, an intrinsic layer, and a top silicon layer doped with a second doping type. The second diode areas are implanted with the second doping type. A dopant concentration in the surface of the second diode areas is at least three times higher than in the first diode areas. The top silicon layer is thermally oxidized to form a thermal silicon oxide layer to provide a bottom Anti-Reflective Coating (ARC) layer. The second diode areas grow thermal silicon oxide thicker as compared to the first diode areas. A top ARC layer is deposited on the bottom ARC layer. First PDs are provided in the first diode areas and second PDs provided in the second diode areas.

Abstract: A power-on reset (POR) circuit includes a first transistor (MPa) having a source coupled to a first supply voltage (VDD) and a gate coupled to a second supply voltage (GND). A resistor (R0) has a first terminal coupled by a depletion mode transistor (JP0) to the second supply voltage and a second terminal coupled to a drain of the first transistor. A Schmitt trigger (20) has an input coupled to receive a first signal (VTRIGGER) on a conductor (14) coupled to the second terminal of the resistor and a terminal of a capacitor (C0), for producing an output voltage (VO) representative of a power-on reset signal (VPOR) in response to an interruption of the first supply voltage (VDD).

Abstract: A process of forming an integrated circuit containing a bipolar transistor and an MOS transistor, by forming a base layer of the bipolar transistor using a non-selective epitaxial process so that the base layer has a single crystalline region on a collector active area and a polycrystalline region on adjacent field oxide, and concurrently implanting the MOS gate layer and the polycrystalline region of the base layer, so that the base-collector junction extends into the substrate less than one-third of the depth of the field oxide, and vertically cumulative doping density of the polycrystalline region of the base layer is between 80 percent and 125 percent of a vertically cumulative doping density of the MOS gate. An integrated circuit containing a bipolar transistor and an MOS transistor formed by the described process.

Abstract: A memory circuit includes a bit cell that receives a word line, complementary bit lines and an array supply voltage; a word line driver coupled to the word line, the word line driver receiving one of the array supply voltage and a periphery supply voltage; and a word line suppression circuit coupled to the word line. The word line suppression circuit includes a diode and a switch coupled in series. The switch is responsive to the array supply voltage. The word line suppression circuit limits a word line voltage to a value lower than the array supply voltage such that the static noise margin (SNM) of the bit cell is increased.

Abstract: In one embodiment, a transmitter includes a binary sequence generator unit configured to provide a sequence of reference signal bits, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to the transmitter and one or more time indices of the sequence. The transmitter also include a mapping unit that transforms the sequence of reference signal bits into a complex reference signal, and a transmit unit configured to transmit the complex reference signal. In another embodiment, a receiver includes a receive unit configured to receive a complex reference signal and a reference signal decoder unit configured to detect a sequence of reference signal bits from the complex reference signal, wherein the sequence is an inseparable function of a cell identification parameter, a cyclic prefix mode corresponding to a transmitter and one or more time indices of the sequence.

Abstract: The resistance of a thin-film resistor is substantially increased by forming the thin-film resistor to line one or more non-conductive trenches. By lining the one or more non-conductive trenches, the overall length of the resistor is increased while still consuming approximately the same surface area as a conventional resistor.

Abstract: An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract: A method of nucleating and growing oxygen precipitates during a pad oxidation process. The nucleating is performed during in the oxidation furnace prior to the pad oxide growth. At least a portion of the growth of the oxygen precipitates occurs during the pad oxide growth. The oxygen precipitates are of sufficient concentration and size in lightly doped p-type wafers for effective gettering of heavy metals is deep submicron transistor, integrated circuit manufacturing flows.

Abstract: An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <100> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing an n-channel extended drain MOS transistor with drift region current flow oriented in the <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa compressive stress. An integrated circuit on a (100) substrate containing a p-channel extended drain MOS transistor with drift region current flow oriented in a <110> direction with stressor RESURF trenches in the drift region. The stressor RESURF trenches have stressor elements with more than 100 MPa tensile stress.