Abstract: A user-heading determining system (10) for pedestrian use includes a multiple-axis accelerometer (110) having acceleration sensors; a device-heading sensor circuit (115) physically situated in a fixed relationship to the accelerometer (110); an electronic circuit (100) operable to generate signals representing components of acceleration sensed by the accelerometer (110) sensors, and to electronically process at least some part of the signals to produce an estimation of attitude of a user motion with respect to the accelerometer, and further to combine the attitude estimation (750, ?) with a device heading estimation (770, ?) responsive to the device-heading sensor circuit, to produce a user heading estimation (780); and an electronic display (190) responsive to the electronic circuit (100) to display information at least in part based on the user heading estimation. Other systems, circuits and processes are also disclosed.

Abstract: One embodiment of the present invention includes a communication network comprises a communication cable having a first wire pair and a second wire pair that both extend between a first end and a second end of the communication cable. The network also comprises at least one power source configured to provide a first supply current through the first wire pair and a second supply current through the second wire pair at the first end of the communication cable. The first supply current and the second supply current can be substantially equal. The network also comprises a first diode bridge and a second diode bridge coupled to the second end of the communication cable and configured to combine the first and second supply currents to provide a combined supply current. The network further comprises a powered device configured to receive the combined supply current.

Abstract: An embodiment of the invention provides a method of detecting the position(s) where sensor(s) are activated on an interactive screen using sparse-activation compressive sensing. Sparse-activation compressive sensing makes use of the situation where the number of simultaneously activated sensors is substantially smaller than the number of sensors (nodes). Because the number of simultaneously activated sensors is substantially smaller than the number of sensors, the number of measurements required for determining which sensors are activated may also be reduced. Because fewer measurements are required when compared with full-scan techniques, less circuitry and power is required to detect the location(s) of activated sensors on an interactive screen.

Abstract: The present invention provides a microstructure device comprising multiple substrates with the components of the device formed on the substrates. In order to maintain uniformity of the gap between the substrates, a plurality of pillars is provided and distributed in the gap so as to prevent decrease of the gap size. The increase of the gap size can be prevented by bonding the pillars to the components of the microstructure. Alternatively, the increase of the gap size can be prevented by maintaining the pressure inside the gap below the pressure under which the microstructure will be in operation. Electrical contact of the substrates on which the micromirrors and electrodes are formed can be made through many ways, such as electrical contact areas, electrical contact pads and electrical contact springs.

Abstract: Logic circuitry and corresponding software instructions for performing functions within the FL function of a Kasumi cipher. An RLAX logic circuit includes a bit-wise AND function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLAX program instruction. An RLOX logic circuit includes a bit-wise OR function, a reorder bus, and a bit-wise exclusive-OR function for generating a destination word from corresponding logic functions of portions of first and second operands, in executing an RLOX program instruction. Plural instances of the logic circuits can be implemented in parallel, to simultaneously operate upon plural data blocks.

Abstract: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of the functional data signals. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports. While operating in a scan mode, a first clock signal is used by the slave transparent latch and a second clock signal is used by the master transparent latch, wherein the first and second clock signals are non-overlapping.

Abstract: In a digital device, activity of (or load on) one or more processors, peripherals and memory buses are measured. A power management framework operated in the digital device bases power settings in the digital device on the measured loads, and accordingly issues power management commands to change power consumption states of one or more of the processors, peripherals and memory buses. Some user applications (termed power aware applications) in the digital device provide a number identifying their application type to the power management framework, which thereby determines the resources required by the application. The power management commands issued by the power management framework ensure provision of the corresponding resources to the application, while also targeting minimization of power consumption in the digital device. In an embodiment, the digital device corresponds to a mobile phone.

Abstract: According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface of a spatial light modular to an image field using a projection system; capturing light from the image field using the projection system, the projection system directing at least a portion of the captured light to the spatial light modulator; and directing at least a portion of the received captured light to an image capture system using the spatial light modulator.

Abstract: A method of forming stressed-channel NMOS transistors and strained-channel PMOS transistors forms p-type source and drain regions before an n-type source and drain dopant is implanted and a stress memorization layer is formed, thereby reducing the stress imparted to the n-channel of the PMOS transistors. In addition, a non-conductive layer is formed after the p-type source and drain regions are formed, but before the n-type dopant is implanted. The non-conductive layer allows shallower n-type implants to be realized, and also serves as a buffer layer for the stress memorization layer.

Abstract: An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of the isolation trench, forming polysilicon sidewalls on the first shallow portion, and then etching the second deeper portion.

Abstract: A microelectromechanical (MEMS) device is fabricated from a wafer having a plurality of die regions with grooves and MEMS components formed on a wafer surface at each die region. A first metal having a relatively high melting temperature is formed on sidewalls of each groove, and a cap is attached at each die region to provide a closed cavity which encloses the grooves and MEMS components. Bottoms of the grooves are opened by thinning the wafer thereby establishing through-hole vias extending through the wafer at each die region, for accessing the cavity for inserting or removing material. The vias are sealed by interacting a second metal having a relatively low melting temperature with the first metal layer to form intermetallic compounds with higher melting temperature that maintain the seal during subsequent lower temperature operations.

Abstract: Conventional routers employ a wired backplane that employs “long reach” serializer/deserializer (SerDes) links, but this type of architecture is complicated, costly, and uses a considerable amount of power. To address some of these issues, a new wireless backplane architecture is provided here. This wireless backplane employs direct millimeter wave links between line cards that replaces the convention, wired switching fabric.

Abstract: A toy building block of a type which may be interconnected with similarly configured blocks has a hollow box-shaped structure having a top with cylindrical stud coupling members, and sides which together with the top define a downwardly opening cavity into which the cylindrical studs of a like configured block may be inserted for frictional interconnection. One or more integrated circuit chips are embedded within the molding material of the block, and leads incorporated within the block studs and sides provide electrical interconnection between blocks when like configured blocks are brought into frictional interengagement. In a described embodiment, components of a digital video recording system are apportioned to different blocks which when interconnected provide the complete system functionality.

Abstract: A method of stressing and screening static random access memory (SRAM) arrays to identify memory cells with bit line side pass transistor defects. After writing initial data states into the memory array under nominal bias conditions, an elevated bias voltage is applied to the memory array, for example to its power supply node. Under the elevated bias voltage, alternating data patterns are written into and read from the memory array for a selected duration. The elevated bias voltage is reduced, and a write screen is performed to identify defective memory cells. The dynamic stress of the repeated writes and reads accelerates early life failures, facilitating the write screen.

Abstract: In an embodiment of the invention, a pipelined memory bank is tested by scanning test patterns into an integrated circuit. Test data is formed from the test patterns and shifted into a scan-in chain in the pipelined memory bank. The test data in the scan-in chain is launched into the inputs of the pipelined memory bank during a first clock cycle. Data from the outputs of the pipelined memory bank is captured in a scan-out chain during a second cycle where the time between the first and second clock cycles is equal to or greater than the read latency of the memory bank.

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: The invention relates to a method of manufacturing an integrated circuit. An electrically resistive layer of a material for serving as a thin film resistor (TFR) is deposited. A first electrically insulating layer is deposited on the electrically resistive layer of the TFR. An electrically conductive layer of an electrically conductive material is deposited. An area is left without the conductive layer and the area overlaps the electrically resistive layer of the TFR. A second electrically insulating layer is deposited on top of the conductive layer. A first VIA opening is etched through the second insulating layer, the area without the conductive layer adjacent to the electrically conductive layer and through the first insulating layer down to the electrically resistive layer of the TFR. A conductive material is deposited in the first VIA opening so as to electrically connect the conductive layer and the electrically resistive layer of the TFR.

Abstract: Various wireless precoding systems and methods are presented. In some embodiments, a wireless transmitter comprises an antenna precoding block, a transform block, and multiple transmit antennas. The antenna precoding block receives frequency coefficients from multiple data streams and distributes the frequency coefficients across multiple transmit signals in accordance with frequency-dependent matrices. The transform block transforms the precoded frequency coefficients into multiple time domain transmit signals to be transmitted by the multiple antennas. The frequency coefficients from multiple data streams may be partitioned into tone groups, and all the frequency coefficients from a given tone group may be redistributed in accordance with a single matrix for that tone group. In some implementations, the frequency coefficients within a tone group for a given data stream may also be precoded. In some alternative embodiments, tone group precoding may be employed in a single channel system.

Abstract: A method for equalizing a received signal is provided. The signal is filtered and transmitted over a channel using an encoding scheme, where the encoding scheme has transmit symbols. This transmitted signal is then shaped such that the filtering and equalization adjust a set of taps in an equalization window so that the taps from the set are substantially equal to one another. Inter-symbol interference is then compensated for in the equalized signal using a speculative DFE with significantly reduced comparator levels.

Abstract: Example embodiments of the systems and methods of dynamic spur mitigation for wireless receivers disclosed herein comprise one or more of a detection module for detecting the presence of a spur and a determination of its frequency, a complex notch filter chain, and a frequency locked loop which ensures that the input spur is notch filtered even if it drifts after detection. When a spur is detected, the frequency of the tone is determined. The spur is then filtered, for example using a phase rotator and a DC separator. The phase rotation is removed in a subsequent stage. The non-DC component from the DC separator is used to track the spur to compensate for any shifting or drifting in the spur.