Abstract: Viterbi decoding is performed on a microcontroller by initializing a state-metric array by executing load instructions to load state-metric data from a memory module into a set of registers in the microcontroller. Butterfly processing on the state-metric array is performed by executing Viterbi processing instructions fetched from a program storage module to manipulate the state-metric (SM) data in the set of registers for each Viterbi butterfly in a stage of Viterbi decoding to form a final set of state-metric data and trace bits. After completing each stage, a final set of state-metric data is stored in the memory module by executing store instructions.

Abstract: A 1149.1 TAP performs at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. In a second embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal. In a third embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states. In a fourth embodiment the at-speed operations are achieved by detecting the TAP's Exit1DR and PauseDR states and inputting these states to a Dual Port Router to control the at-speed operations of a circuit. The improvements are achieved without requiring any additional IC pins beyond the 4 required TAP pins. Devices including the TAP improvements can be operated compliantly in a daisy-chain arrangement with devices that don't include the TAP improvements.

Abstract: An embodiment of the invention provides a method of correcting 2 bits and detecting three bit using an extended bidirectional Hamming code. A data word with length K=2m?1 is received. A code word with length N=2m?1+2m+1 is generated from the data word in accordance with the extended bidirectional Hamming code defined by the following parity check matrix: H = [ 1 1 … 1 1 ? … ? N - 1 1 ? - 1 … ? - N + 1 ] . The number of parity bit is given by (2m+1).

Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

Abstract: An electronic circuit includes a floating gate transistor with a floating gate capacitor. The floating gate transistor can be programmed to be in an ON or an OFF state by charging the floating gate capacitor. The circuit further includes a deactivation capacitor adapted to store a charge sufficient for deactivating the floating gate transistor temporarily. The deactivation capacitor is connectable in series to the floating gate capacitor. A method for deactivating a floating gate transistor temporarily is provided, wherein the floating gate transistor includes a floating gate capacitor. A deactivation capacitor is charged with a charge sufficient for changing the state of the floating gate transistor temporarily. The deactivation capacitor is connected in series to the floating gate capacitor for deactivating the floating gate transistor.

Abstract: An integrated circuit is described that has a substrate with a memory array with dedicated support hardware formed on the substrate. An access wrapper circuit is coupled to address and data lines of the memory array and to control lines of the dedicated support hardware. The wrapper circuit is configured to provide an access port to the memory array. A test controller is formed on the substrate and coupled in parallel with the access wrapper circuit to the address and data lines of the memory array and to the control lines of the dedicated support hardware, wherein the test controller is operable to perform a test of the memory array by manipulating control signals to the support hardware in addition to those required to write data patterns into the memory array and to read the contents of the memory array.

Abstract: This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook sub-sampling in report 1. If CSI mode 2 is selected W1 and W2 are jointly encoded using codebook sub-sampling in report 2.

Abstract: A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.

Abstract: A system includes an actuator configured to generate vibrations for creating tactile feedback to a user. The system also includes a sensor configured to measure the vibrations generated by the actuator. The system further includes a tactile feedback system configured to drive the actuator in order to generate the vibrations. The tactile feedback system is configured to adjust the driving of the actuator in response to measurements from the sensor. The actuator could include a motor configured to drive an eccentric mass, and the sensor could include an accelerometer and/or a gyroscope. Among other things, the tactile feedback system could be configured to over-drive a motor of the actuator until the measurements from the sensor indicate that vibrations are detected by the sensor and to back-drive the motor of the actuator until the measurements from the sensor indicate that no vibrations are detected by the sensor.

Abstract: A spatial light modulator comprises a solid-state chiral material disposed between electrodes such that the polarization direction of the polarized light incident thereto can be controlled through an electrical field established between the electrodes.

Abstract: A system for, and method of, generating multicolor scan lines and a multicolor projection video display (PVD) incorporating the system or the method. In one embodiment, the system includes: (1) light sources that emit light of different colors at different emission locations and (2) first and second lenses having lenticular arrays associated therewith and configured to receive the light of the different colors and generate multicolor scan lines therefrom, the emission locations separated by different distances from the first lens.

Abstract: An apparatus and a method for a programmable timing in digital integrated circuits implementing peak current mode controlled power converters are disclosed. The programmable dead-time is implemented by means implemented in hardware, software, and combination of hardware and software, carrying out setting a second timer value; setting a third timer value with respect to the second timer value; detecting a reset event; reloading a second counter from a current timer value to the second timer value upon detecting the reset event; resetting a second pulse width modulated waveform amplitude from a second amplitude value to a first amplitude value upon detecting the reset event; and setting a first pulse width modulated waveform from a first amplitude value to a second value upon the second counter reaching a third value.

Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.

Abstract: In an LDMOS device leakage and forward conduction parameters are adjusted by integrating an Schottky diode into the LDMOS by substituting one or more n+ source regions with Schottky diodes.

Abstract: An isolation trench in a substrate of a semiconductor device includes a first shallow portion with a dielectric sidewall and a second deeper portion without a dielectric sidewall. The isolation trench is formed by forming a first shallow portion of the trench, forming dielectric sidewalls on the first shallow portion, and then etching the substrate below the first shallow portion to form the second deeper portion. Shallow isolation trenches may be formed simultaneously with the etching of the second deeper portion.

Abstract: Various embodiments of circuits and methods for enabling a slew rate programmability and compensation of input/output circuits are provided. The circuit includes a delay code generation circuit and at least one input/output (I/O) circuit. The delay code generation circuit is configured to receive a clock signal and a delay factor and generate a compensated delay code based on the clock signal or a combination of the delay factor and the clock signal. The I/O circuit includes a plurality of delay lines associated, integrated or communicatively associated with the delay code generation circuit and is configured to program the plurality of delay lines so as to generate a predetermined delay corresponding to the compensated delay code in order to achieve a predetermined slew rate of the I/O circuit.

Abstract: Circuitry and methods for measuring capacitive mismatch with improved precision. The capacitors under measurement are connected in series in a voltage divider, with the node common to both capacitors connected to the gate of a source follower transistor. In one disclosed embodiment of the invention, a ramped voltage is applied to the drain of the source follower transistor simultaneously with the ramped voltage applied to the voltage divider; the slope of the ramped drain voltage is at the nominal slope of the voltage at the common node of the voltage divider. In another embodiment, a second transistor in saturation has its gate coupled to the source of the source follower device, and its source connected to the drain of the source follower device in series with a constant voltage drop. The drain-to-source voltage of the source follower device is thus held constant in each embodiment, improving precision of the measurement.

Abstract: A method includes testing to failure a plurality of semiconductor test structures, measuring a parameter of each semiconductor test structure after experiencing a failure, and generating a cumulative probability distribution function (CPDF) of cumulative probability versus the measured parameter after failure for the plurality of semiconductor test structures. The method further includes performing simulations for a circuit having an area using a model of a transistor that mimics the failure to determine a parameter threshold value that defines a minimum acceptable performance level of the circuit, determining a cumulative probability value from the CPDF that a transistor will not have the parameter at a level below the parameter threshold value, adjusting a value of the area of the circuit based on the cumulative probability value, and computing a first reliability value based on the adjusted area value.

Abstract: A method for encoding a picture of a video sequence in a bit stream that constrains tile processing overhead is provided. The method includes computing a maximum tile rate for the video sequence, computing a maximum number of tiles for the picture based on the maximum tile rate, and encoding the picture wherein a number of tiles used to encode the picture is enforced to be no more than the maximum number of tiles.

Abstract: A switching regulator comprising a droop amplifier responsive to a reference voltage and a feedback voltage to generate a droop voltage. The droop amplifier includes a boost circuit configurable to increase a transconductance of the droop amplifier during an upward transition of the reference voltage. The switching regulator further includes a comparator responsive to the droop voltage and a current sense signal. The comparator is configured to initiate switching in the switching regulator.