Abstract: A method for encoding a picture of a video sequence in a bit stream that constrains tile processing overhead is provided. The method includes computing a maximum tile rate for the video sequence, computing a maximum number of tiles for the picture based on the maximum tile rate, and encoding the picture wherein a number of tiles used to encode the picture is enforced to be no more than the maximum number of tiles.

Abstract: A prescaling counter includes a prescaling unit and a counter. The prescaling unit includes a programmable divider that is arranged to divide an event clock that includes signaled events to generate a prescaled clock in response to a prescaling value. The counter includes a register that includes a lower count register and an upper count register for generating a count result. The counter is arranged to increment the lower count register in response to the prescaled clock and to increment the upper count register in response to a terminal condition in the lower count register. The prescaling value is generated in response to the upper count register.

Abstract: A method and apparatus for coordinating a multi-point wireless transmission between a plurality of geographically separated transmission points and at least one user equipment.

Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.

Abstract: A query is generated for determining a correlation between an advertisement and a person who interacted with a merchant. The query includes an image of the person. In response to the query, a determination is made about whether the correlation exists between the image and a face that has given attention to the advertisement. In response to determining that the correlation exists, a report of the correlation is generated for the merchant.

Abstract: Offset calibration technique to improve performance of band gap voltage reference. An example of a bandgap reference source includes an output resistor, a first and second transistors and a differential amplifier. A positive-input calibration phase switch is in communication with a positive amplifier input, a emitter of the first and second transistor and a negative-input calibration phase switch in communication with the negative amplifier input, the emitter of the first and second transistor. A positive-output calibration phase switch is in communication with the positive amplifier output, the first and second terminal of the output resistor and a negative-output calibration phase switch is in communication with the negative amplifier output, the first and second terminal of the output resistor. An adjustable resistance is in communication with the emitter of the first transistor, the emitter of the second transistor, and the second terminal of the output resistor.

Abstract: A first radio receiver may be configured to receive an RF signal from an RF port and may comprise a first cascode amplifier configured to provide a primary RF signal on a primary path for processing by the first RF receiver and a bypass RF signal on a bypass path. A second radio receiver may be configured to receive a sum of the bypass RF signal and an amplified primary RF signal. As a result, the second radio receiver is coupled to the same RF port and the signal received by the second receiver is maintained constant irrespective of the RF signal current drawn by the first receiver. The product of the impedance of the tuned load of the first radio receiver and the gain of the amplifier amplifying the primary RF signal is set to unity.

Abstract: This invention allows code emulation in a memory system by implementing a fixed location and size emulation segment that is only accessible to emulation requests, and may be mapped to any area of the physical memory space by the Extended Memory Controller. All areas of the memory space are visible to the emulation process, whether there is a functional segment mapped to that area or not.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes an input padding module configured to provide padded bits having padding bits added to payload bits for one or more control channels, and a scrambling module configured to apply a masking sequence to one or more of the padded bits to generate scrambled bits. Additionally, the transmitter also includes an encoding module configured to perform forward error correction encoding and rate matching on the scrambled bits to obtain a required number of control channel output bits, and a transmit module configured to transmit the control channel output bits for one or more control channels.

Abstract: Supply voltage sequencing circuitry includes a first sequencer (10-1) that produces an active level of a Power Good signal PG if a first supply voltage VOUT1 exceeds an upper threshold V90% while a control signal EN_PG is active, and produces an inactive level of PG if EN_PG is inactive. The PG level is latched when a control signal EN is inactive. A Power Down signal PD is produced if VOUT1 is less than a lower threshold V10% while EN is inactive. An active level of PD is produced when EN is active. A power-up sequence of supply voltages VOUT1, VOUT2, and VOUT3 monitored by the first sequencer and similar second (10-2) and third (10-3) sequencers, respectively, is determined by connection of PG of each of the first and second sequencers to control the supply voltage monitored by the next sequencer.

Abstract: A system comprising a pre-power amplifier and a hardware device which is configured to predistort an amplitude input signal by comparing interpolated data places, determined by comparing the input signal with data from a LUT, coming from a LUT with the amplitude input signal and choosing the closest input data place to the amplitude input signal to produce an amplitude predistortion output signal. The LUT contains predistortion data associated with the pre-power amplifier. The amplitude input signal is multiplied and scaled prior to being compared with the data in the LUT. A second LUT is used to predistort a phase input signal and the phase predistortion output signal is combined in the pre-power amplifier with the amplitude predistortion output signal. The system may be implemented in a mobile communications device.

Abstract: A prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request. In response per-memory bank logic promotes the priority of the prefetch request to that of a read request. If the prefetch request is still waiting to win arbitration, this upgrade in priority increases the likelihood of gaining access generally reducing the latency. If the prefetch request had already gained access through arbitration, the upgrade has no effect. This thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address.

Abstract: A voltage clamping circuit includes a current source having a fixed current source and a variable current source and a variable resistor receiving current from the current source. The variable resistor varies its resistance in response to an environmental operating condition. The voltage clamping circuit also includes an amplifier configured to compare a sensor node voltage with a reference voltage, the sensor node voltage being in communication with the voltage drop across the variable resistor. The amplifier is configured and connected to provide a control output to control the variable current source to modify current output from the variable current source to at least in part prevent the sensor node voltage from exceeding a reference voltage when certain operating conditions are present.

Abstract: To achieve peak acoustic and power performance, the coil or applied current should be in phase or substantially aligned with the back electromotive force (back-EMF) voltage. However, there are generally phase differences between the applied current and back-EMF voltage that are induced by the impedance of the brushless DC motor (which can vary based on conditions, such as temperature and motor speed). Traditionally, compensation for these phase differences was provided manually and on an as-needed basis. Here, however, a system and method are provided that automatically perform a commutation advance by incrementally adjusting a drive signal over successive commutation cycles when the applied current and back-EMF voltage are misaligned.

Abstract: A high-voltage driver amplifier for piezo haptics comprises an input amplifier having a gain greater than one, a first amplifier of an amplifier pair coupled to an output of the input amplifier, a second amplifier of the amplifier pair coupled to the output of the input amplifier, a first impedance coupled between an output of the first amplifier of the amplifier pair and an input of the input amplifier, and a second impedance coupled between the output of the first amplifier of the amplifier pair coupled to an output of the second amplifier of the amplifier pair. A substantially capacitive load is coupled to the output of the second amplifier. The substantially capacitive load is a piezo-capacitance, wherein the piezo-capacitance is employed in haptics. The second impedance, a shunt impedance, allows for a feedback of output variations between the first amplifier and the second amplifier over the first impedance.

Abstract: This invention is a data processing system with a data cache. The cache controller responds to a cache miss requiring allocation by pre-allocating a way in the set to an allocation request according to said least recently used indication of said ways and then update the least recently used indication of remaining ways of the set. This permits read allocate requests to the same set to proceed without introducing processing stalls due to way contention. This also allows multiple outstanding allocate requests to the same set and way combination. The cache also compares the address of a newly received allocation request to stall this allocation request if the address matches an address of any pending allocation request.

Abstract: An apparatus is provided. The apparatus comprises a substrate and a circuit trace. The substrate includes a region that is adapted to receive a discrete component, a metal layer, a dielectric layer formed over the metal layer, a window formed in the metal layer that underlies the region, and a conductive strap that extends across the window. The circuit trace is formed on the dielectric layer and is discontinuous across the region.

Abstract: Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

Abstract: A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

Abstract: A controller for controlling a power chain in an electronic device can be used in either of two different applications. The first application requires the controller to produce drive signals for driving discrete power MOSFETs within the power chain. The second application requires the controller to produce an output PWM signal to control an integrated circuit having power MOSFETs integrated with MOSFET drivers within the power chain. The controller generally includes a sensor that detects which of the two applications the controller is in. The controller also generally includes outputs that produce, when the controller is in the first application, the drive signals for driving the discrete power MOSFETs. But when the controller is in the second application, one of the outputs is used to produce the output PWM signal for controlling the integrated circuit.