Abstract: An integrated circuit includes an extended drain MOS transistor. The substrate of the integrated circuit has a lower layer with a first conductivity type. A drain well of the extended drain MOS transistor has the first conductivity type. The drain well is separated from the lower layer by a drain isolation well having a second, opposite, conductivity type. A source region of the extended drain MOS transistor is separated from the lower layer by a body well having the second conductivity type. Both the drain isolation well and the body well contact the lower layer. An average dopant density of the second conductivity type in the drain isolation well is less than an average dopant density of the second conductivity type in the body well.

Abstract: A chopper amplifier circuit includes a first amplifier path with chopper circuitry, a switched-capacitor filter, and multiple gain stages. The chopper amplifier circuit also includes a second amplifier path with a feed-forward gain stage. A chopping frequency of the chopper circuitry is greater than a threshold frequency at which the second amplifier path is used instead of the first amplifier path.

Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.

Abstract: An example system comprises: a power transistor comprising a gate, a first terminal, and a second terminal; a transistor comprising a gate, a first terminal, and a second terminal coupled to the gate of the power transistor; a capacitive divider coupled to the first terminal of the power transistor and the gate of the transistor; and a resistive divider coupled to the first terminal of the power transistor and the gate of the transistor.

Abstract: A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

Abstract: Disclosed examples include integrated circuits, merge circuits and methods of processing multiple-exposure image data, in which a single pre-processing circuit is used for pre-processing first input exposure data associated with a first exposure of the image, and then for pre-processing second input exposure data associated with a second exposure of the image, and the first and second pre-processed exposure data are merged to generate merged image data for tone mapping and other post-processing. An example merge circuit includes a configurable gain circuit to apply a gain to the first and/or second exposure data, as well as a configurable weighting circuit with a weight calculation circuit and a motion adaptive filter circuit to compute a first and second weight values for merging the pre-processed first and second exposure data.

Abstract: A power factor correction circuit includes a power transistor, an inductor, and detection circuitry. The inductor is coupled to a drain terminal of the power transistor. The detection circuitry is coupled to the drain terminal of the power transistor. The detection circuitry is configured to determine an input voltage applied to the inductor based on resonant ringing of voltage at the drain terminal, and to detect a valley in the voltage at the drain terminal based on the input voltage applied to the inductor.

Abstract: A power source multiplexer includes a first switch circuit connected between a first input voltage source node and an output voltage node. A second switch circuit is connected between a second input voltage source node and the output voltage node. A driver circuit is configured to provide a steady-state current to drive one of the first or second switch circuits to electrically connect the respective input voltage source node to the output voltage node. A boost circuit is configured to boost the steady-state current for a switching time interval when switching from one of the input voltage source nodes being connected to the output node to the other of the input voltage source nodes being connected to the output voltage node.

Abstract: A system and method for calibrating a pulse width modulation (PWM) signal that extends the on time by a higher resolution increment. The system comprises a PWM generator that receives a VDDIO rail to generate first and second PWM signals, the second PWM signal having an on time extended by the higher resolution increment having a commanded length. The system further comprises a VDDIO circuit that receives the VDDIO rail and outputs a VDDIO signal. First and second analog-to-digital converters are configured to generate a first and second sets of PWM samples and first and second sets of VDDIO samples. A microcontroller is configured to calculate an actual increment length based on the samples, and to compensate for a difference between the commanded length and the actual increment length.

Abstract: An electronic device includes a first circuit (111) operable to generate at least a first and a second channel quality indicator (CQI) vector associated with a plurality of subbands for each of at least first and second spatial codewords respectively and generate a first and a second reference CQI for the first and second spatial codewords, and operable to generate a first and a second differential subbands CQI vector for each spatial codeword and generate a differential between the second reference CQI and the first reference CQI, and further operable to form a CQI report derived from the first and the second differential subbands CQI vector for each spatial codeword as well as the differential between the second reference CQI and the first reference CQI; and a second circuit (113) operable to initiate transmission of a signal communicating the CQI report. Other electronic devices, processes and systems are also disclosed.

Abstract: A load switch circuit implemented on an IC chip includes a first node for coupling to an input voltage, a second node for coupling to an external load, first and second capacitor nodes for coupling to first and second terminals of an external capacitor, and a first PFET coupled between the first node and the second node to control an output voltage to the external load. The load switch circuit also includes a driver circuit having a first NFET that has a drain coupled to the first node and a source coupled to a gate of the first PFET. A slew-rate-control circuit is coupled to a gate of the first NFET and includes the first capacitor node, which is coupled to the gate of the first NFET, and the second capacitor node, which is coupled to the second node.

Abstract: An apparatus to prevent supply-to-ground current in a comparator is disclosed. The apparatus includes circuitry to determine if first and second output nodes of the comparator have respectively reached first and second logic levels, and circuitry responsive to a determination that the voltage at the first and second output nodes of the comparator has reached the first and second logic levels, to generate a signal. In addition, the apparatus includes circuitry to supply the signal to a transistor, the signal to turn off the transistor and prevent the flow of supply-to-ground current through the comparator.

Abstract: A clock apparatus, with: (i) a gas cell, including a cavity including a sealed interior for providing a signal waveguide; (ii) a first apparatus for providing a first electromagnetic wave to travel in the cavity and along a first direction; (iii) a second apparatus for providing a second electromagnetic wave to travel in the cavity and along a second direction opposite the first direction; (iv) a dipolar gas inside the sealed interior of the cavity; and (v) receiving apparatus for detecting an amount of energy in the second electromagnetic wave after the second electromagnetic wave passes through the dipolar gas.

Abstract: An illumination system includes at least first and second laser illumination sources. A down converter material emits light when illuminated by one or more of the laser illumination sources. The first laser illumination source is arranged to illuminate only a first portion of the down converter material. The second laser illumination source is arranged to illuminate only a second portion of the down converter material. Control circuitry causes the first laser illumination source to adaptively vary a first intensity of illuminating the first portion of the down converter material, causes the second laser illumination source to adaptively vary a second intensity of illuminating the second portion of the down converter material, and causes the light modulator to allow a selected amount of the down converter material's emitted light to be projected from the system.

Abstract: An electronic device test system includes a contactor having probe pairs with first and second conductive probes to couple to a respective conductive feature of a packaged electronic device or wafer die region. The system also includes a test circuit having a voltage source to provide a common mode voltage signal; a first buffer with a first input coupled to an output of the voltage source, an output coupled to a first conductive probe of a first probe pair, and a second input coupled to a second conductive probe of the first probe pair; and a second buffer with a first input coupled to the output of the voltage source, an output coupled to a first conductive probe of a second probe pair, and a second input coupled to a second conductive probe of the second probe pair.

Abstract: In described examples, a method for detecting voice activity includes: receiving a first input signal containing noise; sampling the first input signal to form noise samples; determining a first value corresponding to the noise samples; subsequently receiving a second input signal; sampling the second input signal to form second signal samples; determining a second value corresponding to the second signal samples; forming a ratio of the second value to the first value; comparing the ratio to a predetermined threshold value; and responsive to the comparing, indicating whether voice activity is detected in the second input signal.

Abstract: As an example, a circuit is provided. The circuit includes an ESD (electrostatic discharge) clamping circuit with a control signal controlling clamping operations of the ESD clamping circuit. The circuit further includes a counter coupled to the control signal of the ESD clamping circuit. The counter produces a set of output signals responsive to the control signal. The circuit also includes a communications interface for coupling to the set of output signals of the counter. The communications interface also couples to communications circuitry external to the circuit.

Abstract: A current detection system includes an inductor and a detection circuit coupled across the inductor. The inductor is configured to receive an input signal that includes an input current and generate a voltage across the inductor. The current detection circuit includes a sensing network and a transconductance amplifier. The sensing network includes a capacitor and is configured to monitor a voltage across the inductor. The transconductance amplifier is configured to receive a differential voltage indicative of a voltage drop across the capacitor and output a differential output current proportional to the differential voltage.

Abstract: In various examples, a method and apparatus are provided to achieve dynamic biasing to mitigate electrical stress. Described examples include a device includes a first resistor portion having a first terminal and a second terminal, and a second resistor portion having a third terminal and a fourth terminal. The device also includes a well in a substrate proximate to the first resistor portion and the second resistor portion and an insulating layer between the well and the first resistor portion and the second resistor portion. The device also includes a transistor having a control terminal coupled to the second terminal of the first resistor portion and the third terminal of the second resistor portion, the transistor having a first current-handling terminal coupled to a first voltage and a second current-handling terminal coupled to a current source and to the well.

Abstract: In described examples, circuitry for saving and restoring a design block state includes first memories configured to receive, and store in different first memories in a first order, different portions of first data; and a second memory coupled to first memories. First memories with the most memory cells have N memory cells. First memories with fewer memory cells have M memory cells. When saving state, first data from different first memories is written in a second order to different corresponding regions of the second memory as second data. The second order repeats portions of the first data stored in sequentially first N mod M cells, determined using the first order, of corresponding first memories with fewer cells. When restoring state, second data is read from the second memory and stored, in the first order, in corresponding first memories; repeated portions are repeatedly stored in corresponding first memories with fewer cells.