Abstract: In a described example a device includes: a first corner formed between a circuit side surface of a semiconductor die and a first sidewall formed with a first depth extending along a side of the semiconductor die from the circuit side surface; a ledge having a planar surface formed parallel to the circuit side surface of the semiconductor die formed at the first depth from the circuit side surface at the first corner, and being perpendicular to the first sidewall; a second corner formed by an intersection of the planar surface of the ledge and a scribe lane sidewall of the semiconductor die, forming a second sidewall perpendicular to the circuit side surface; and portions of the circuit side surface of the semiconductor die, the first corner, the first sidewall, and the planar surface of the ledge covered by a passivation layer.

Abstract: In described examples, an image-generating panel is arranged for modulating a projection beam to include a modulated optical image. A cooling device is arranged to transfer heat received from the image-generating panel to a heat sink. The cooling device is arranged to receive the projection beam on a first side and to transmit the projection beam from a second side. The heat received from the image-generating panel can include heat generated by the image-generating panel in response to incidental sunlight.

Abstract: This invention is a streaming engine employed in a digital signal processor. A fixed data stream sequence is specified by a control register. The streaming engine fetches stream data ahead of use by a central processing unit and stores it in a stream buffer. Upon occurrence of a fault reading data from memory, the streaming engine identifies the data element triggering the fault preferably storing this address in a fault address register. The streaming engine defers signaling the fault to the central processing unit until this data element is used as an operand. If the data element is never used by the central processing unit, the streaming engine never signals the fault. The streaming engine preferably stores data identifying the fault in a fault source register. The fault address register and the fault source register are preferably extended control registers accessible only via a debugger.

Abstract: A method of testing a device under test, the device under test comprising a scan chain having a number of storage elements. The method determines a representation of toggling events in a test sequence, where the test sequence is for testing the scan chain. The method also selectively times input of a bit sequence, corresponding to the test sequence, to a first storage element in the number of storage elements, and through the scan chain, in response to the determining step.

Abstract: Disclosed examples include an ESD protection circuit, including a transistor operative according to a control voltage signal at a control node to selectively conduct current from a protected node to a reference node during an ESD event, as well as a resistor connected between the control node and the reference node, a capacitor connected between the control node and an internal node, and a diode with an anode connected to the protected node and a cathode connected to the internal node to allow charging current to flow from the protected node to charge the capacitor and to provide a high impedance to the internal node to prevent or mitigate flow of leakage current from the internal node to the protected node to raise a trigger voltage of the protection circuit during normal operation.

Abstract: A strain gauge sensor includes a substrate, at least one resistor comprising a magnetoresistive material on the substrate. The magnetoresistive material exhibits a magnetostriction coefficient ? that is greater than or equal to () |2| parts per million (ppm) and an anisotropic magnetoresistance effect with an anisotropic magnetoresistance of greater than or equal to () 2% ? R/R. The strain gauge sensor consists of a single layer of the magnetoresistive material. At least a first contact to the resistor provides a sensor input and a second contact to the resistor provides a sensor output.

Abstract: A semiconductor device includes a first body having a first coefficient of thermal expansion (CTE) and a first surface, a third body having a third CTE and a third surface facing the first surface, and a fourth surface at an angle with respect to the third surface defining an edge of the third body, and a second body having a second CTE higher than the first and the third CTE, the second body contacting the first and the third surfaces. A post having a fourth CTE lower than the second CTE, transects the second body and contacts the edge.

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

Abstract: A BLE network includes a first piconet including a first master scanner and a first group of low-power slave/advertisers for transmitting wireless advertisements. Circuitry in the first master/scanner wirelessly scans to detect an advertisement transmitted by a first slave/advertiser of the first group and transmits a connection request in response to the detecting, and transmits a schedule for subsequent advertisements after an initial advertisement by the first slave/advertiser. Circuitry in the first slave/advertiser transmits the initial advertisement, receives an acceptance a resulting connection request, establishes association with the first master scanner, and then causes the first slave/advertiser to go to sleep, to wake up and transmit subsequent advertisements according to the schedule and accept resulting connection requests, and transmits available data to the first master/scanner, and goes back to sleep.

Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

Abstract: A signal path linearizer for PAM4 SerDes communications compensates (including pre-compensates) for signal path nonlinearities. The linearizer can be configured with first and second differential gm stages, the first differential gm stage to provide a DC gain, and the second differential gm stage to introduce a defined nonlinear adjustment in DC gain by adding to or subtracting from the DC gain of the first differential gm stage. The differential gm stages can be configured to generate a compensated PAM4 signal with the combined DC gain providing a nonlinear wideband gain adjustment to compensate for nonlinearities in the PAM4 signal path. Compensation range can be increased by selective degeneration, and the compensation region can be shifted by selectively introducing input offset(s).

Abstract: A radar system is provided that includes a first radar transceiver integrated circuit (IC) including transmission signal generation circuitry operable to generate a continuous wave signal and a first transmit channel coupled to the transmission generation circuitry to receive the continuous wave signal and transmit a test signal based on the continuous wave signal, and a second radar transceiver IC including a first receive channel coupled to an output of the first transmit channel of the first radar transceiver IC via a loopback path to receive the test signal from first the transmit channel, the second radar transceiver IC operable to measure phase response in the test signal.

Abstract: An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

Abstract: Methods and devices for detecting USB devices attached to a USB charging port including a USB port having a first data line D+, a second data line D?, and a power line are disclosed. A USB device is attached to the USB port; applying power to the USB device by the power line; applying a first voltage to the line D+ at the USB port by a first impedance; applying a second voltage to the line D? at the USB port by a second impedance. The voltages on the line D+ and the line D? are then monitored at the USB port. If the voltage on the line D+ is approximately equal to a first predetermined value for a predetermined period and the voltage on the line D? is below a second predetermined value, then the USB device is determined to be of an alpha type device.

Abstract: A testing device for FMCW radar includes an input for receiving a chirp signal generated by the radar. An IQ down-converter coupled to the input down-converts the chirp signal. A digitizer extracts digitized IQ signals from the down-converted chirp signal. A processor coupled to the digitizer determines at least one of frequency linearity and phase noise of the chirp signal.

Abstract: A system includes: a reference buffer coupled to an input supply voltage; an analog-to-digital converter (ADC) coupled to an output of the reference buffer; and an output capacitor coupled between the output of the reference buffer and a ground node. The reference buffer includes: an integrator; an internal capacitor coupled between an output of the integrator and the ground node; a first gain stage with an input coupled to the output of the reference buffer; and a second gain stage with an input coupled to the output of the integrator. The output of the first gain stage is combined with the output of the integrator using a combine circuit.

Abstract: A switchable array micro-lattice comprises a plurality of interconnected units wherein the units are formed of graphene tubes. JFET gates are provided in selected members of the micro-lattice. Gate connectors are routed from an external surface of an integrated circuit (IC) through openings in the micro-lattice to permit control of the JFET gates.

Abstract: A microelectronic device has a substrate attached to a substrate pad on a first face of the substrate, and a component attached to the substrate on the first face. The substrate has a component placement guide on the first face. The substrate has a singulation guide on a second face of the substrate, located opposite from the first face. The microelectronic device is formed by attaching the component to a substrate sheet which contains the substrate. The substrate sheet with the component is mounted on a singulation film so that the component contacts the singulation film. The singulation guide on the second face of the substrate is located opposite from the singulation film. The substrate is singulated from the substrate sheet. The substrate with the component is attached to the substrate pad on the first face of the substrate, adjacent to the component.

Abstract: A microelectronic device has a first die attached to a first die pad, and a second die attached to a second die pad. A magnetically permeable member is attached to a first coupler pad and a second coupler pad. A coupler component is attached to the magnetically permeable member. The first die pad, the second die pad, the first coupler pad, the second coupler pad, and the magnetically permeable member are electrically conductive. The first coupler pad is electrically isolated from the first die, from the second coupler pad, and from external leads of the microelectronic device. The second coupler pad is electrically isolated from the first die and from the external leads. The first die and the second die are electrically coupled to the coupler component. A package structure contains at least portions of the components of the microelectronic device and extends to the external leads.

Abstract: A rectangular via extending between interconnects in different metallization levels can have a planform with a width equal to the width of the interconnects and a length equal to twice the width and can be aligned along a long dimension with a length of the upper interconnect. In an integrated circuit layout, the planform can be centered over the width of the lower interconnect, allowing for misalignment during fabrication while maintaining a robust electrical connection. The bottom of the via may be aligned with an upper surface of the lower interconnect or may include portions below the lower interconnect's upper surface. Fewer adjacent routing tracks are blocked by use of the rectangular via than would be blocked using redundant square vias, while ensuring reliability of the electrical connection despite potential misalignment during fabrication.