Abstract: In an embodiment, a circuit includes a Direct Current (DC)-DC buck-boost converter and a controller. The controller includes an error amplifier configured to receive a feedback signal responsive to an output signal of the buck-boost converter. The error amplifier is configured to compare the feedback signal and a reference signal to generate an error signal. The controller includes a modulator circuit that is configured to receive the error signal and compare the error signal with a periodic ramp signal to generate a modulated signal. The controller further includes a digital logic block to generate switching signals in response to the modulated signal that is fed to the buck-boost converter to control the output signal of the buck-boost converter. The controller includes a capacitance multiplier circuit coupled to the output of the error amplifier to configure a dominant pole so as to compensate the buck-boost converter.

Abstract: Described herein is a technology or a method for fabricating a flip-chip on lead (FOL) semiconductor package. A lead frame includes an edge on surface that has a geometric shape that provides a radial and uniform distribution of electric fields. By placing the formed geometric shape along an active die of a semiconductor chip, the electric fields that are present in between the lead frame and the semiconductor chip are uniformly concentrated.

Abstract: A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

Abstract: An apparatus includes a power transistor to conduct a load current from a supply voltage node to an output node and a current sense circuit coupled to the power transistor. The current sense circuit generates a current sense current proportional to the load current. A temperature sense circuit is included to generate a temperature sense voltage proportional to the temperature of the power FET. A thermal limit circuit is coupled to the temperature sense circuit. A current limit circuit is coupled to the current sense circuit and to the thermal limit circuit. The current limit circuit generates a control signal on a current limit circuit output node. The control signal is responsive to the current sense current and to a first current from the thermal limit circuit. The current limit circuit output node is coupled to a control input of the power transistor.

Abstract: A circuit comprises a multiphase gate driver to be coupled to a multiphase inverter for driving a multiphase motor. For each phase, the multi-phase gate driver is to, in accordance with a pulse width modulation (PWM) control signal, turn on and off a high side transistor of a given pair of high and low side transistors of the multiphase inverter, discontinue the PWM control signal turn to the high side transistor of the given pair and turn off the high side transistor of the given pair, and turn on the low side transistor of the given pair until a current level through the low side transistor falls below a threshold, at which time, turn off the low side transistor.

Abstract: Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. The method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size.

Abstract: A lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad, exposed side walls, and exposed back sides of the terminals. A solder wetable metal or metal alloy plating layer is on the back side and on the exposed the walls of the terminals. The exposed thermal pad and the back side of the terminals each include a contact region which lacks the plating layer.

Abstract: An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

Abstract: In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.

Abstract: A system includes a downstream facing port (DFP) coupled to a video source, an upstream facing port (UFP) coupled to a video sink, and a cable. The cable includes a first end that is connected to the DFP and a second end that is connected to the UFP. The cable is configured to carry a differential auxiliary transmission signal and detect polarity in the differential auxiliary transmission signal.

Abstract: A system, method and apparatus for tuning an internal oscillator to a desired frequency F1 is shown and uses an RC delay element that comprises a resistor, a capacitor and a comparator. The method includes receiving a clock signal from an oscillator to be tuned, triggering charging of the RC delay element, and N clock cycles after triggering the charging, the method determines whether the charge on the precision RC delay element is higher than or lower than a reference voltage. Correction to the clock frequency is based on the results.

Abstract: The disclosed principles provide a stress buffer layer between an IC die and heat spreader used to dissipate heat from the die. The stress buffer layer comprises distributed pairs of conductive pads and a corresponding set of conductive posts formed on the conductive pads. In one embodiment, the stress buffer layer may comprise conductive pads laterally distributed over non-electrically conducting surfaces of an embedded IC die to thermally conduct heat from the IC die. In addition, such a stress buffer layer may comprise conductive posts laterally distributed and formed directly on each of the conductive pads. Each of the conductive posts thermally conduct heat from respective conductive pads. In addition, each conductive post may have a lateral width less than a lateral width of its corresponding conductive pad. A heat spreader is then formed over the conductive posts which thermally conducts heat from the conductive posts through the heat spreader.

Abstract: An apparatus includes a temperature sensor, a pressure sensor, a communication interface, and a hardware controller. The hardware controller may detect a door open and close event for a refrigeration unit and receives temperature readings from the temperature sensor and pressure readings from the pressure sensor. The hardware controller determines whether a performance level of the seal has fallen below a threshold level based on the temperature and pressure readings and transmits a signal through the communication interface responsive to a determination that the performance level of the seal has fallen below the threshold level.

Abstract: A converter circuit includes a power stage circuit configured to convert an input voltage received by an inductor to an output voltage provided at an output; a control circuit configured to generate input pulses to control the power stage circuit; a slope compensation circuit configured to provide a compensation signal to the control circuit for overcoming a sub-harmonic oscillation in the converter circuit, wherein the control circuit is configured to generate the input pulses based at least in part on the compensation signal; a slope compensation adjustment circuit configured to determine a rate of change of a current at the inductor and to provide a slope compensation adjustment signal based on the determined rate of change; and a modulation circuit configured to modulate the compensation signal with the slope compensation adjustment signal to produce the adjusted slope compensation signal.

Abstract: The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.

Abstract: A circuit for digital filtering an analog signal converted to digital, including an analog circuit to generate an analog signal, the analog signal including phase and/or gain errors. An analog-to-digital converter (ADC) to convert the analog signal to a digital signal output to a digital signal path. A frequency-dependent corrector filter included in the digital signal path, and configured as a parameterized filter, the parameterized filter configurable based on the DSA control signal with at least one complex filter parameter for each DSA attenuation step, to correct frequency-dependent errors in phase and/or gain.

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

Abstract: A projector includes a semiconductor die including a digital micromirror device; and a first integral optical layer attached to the semiconductor die. The first integral optical layer includes a first optical lens and a first diffractive optical element. A second integral optical layer is attached to the first integral optical layer. The second integral optical layer includes an aperture stop and a second diffractive optical element. A third integral optical layer is attached to the second integral optical layer. The third integral optical layer includes a second optical lens and a light source mount. The semiconductor die, the first integral optical layer, the second integral optical layer and the third integral optical layer are stacked to form an optical path through the first and second diffractive optical elements, reflect off the digital micromirror device, and pass through the first optical lens, the aperture stop and the second lens.

Abstract: A device for averaging a sensed current includes a sampling circuit that samples at least two sampling points of each cycle of a front-end alternating current (AC) sensed signal. The two sampling points is substantially symmetrical with respect to a midpoint of each respective cycle of the front-end AC sensed signal. The device also includes a timing circuit that controls a timing of the sampling circuit to sample the front-end AC sensed signal on the at least two sampling points based on a timing signal generated by the timing circuit. The device further includes an averaging circuit that averages the two sampling points for a given cycle of the front-end AC sensed signal to produce an average sensed current.

Abstract: A chuck apparatus includes a nozzle with a first end configured to engage a device under test (DUT), and a clamp extending around a portion of the nozzle proximate the first end. The clamp includes a recess to receive the DUT, and an engagement surface in the recess to engage the DUT. The chuck apparatus also includes a spring that biases a surface of the clamp toward the first end of the nozzle. A method includes translating a chuck to engage a nozzle with a DUT, further translating the chuck to engage and self-align an engagement surface of a spring mounted clamp with the DUT, further translating the chuck to seat the DUT in the spring mounted clamp, translating the chuck with the DUT to a contactor and translating the chuck with the DUT to engage conductive features of the DUT with conductive probes of the contactor.