Abstract: A re-sampler comprises a first CSD multiplier configured to receive input samples, a first accumulator coupled to the first CSD multiplier and configured to form a first MAC unit with the first CSD multiplier, a second CSD multiplier configured to receive the input samples, and a second accumulator coupled to the second CSD multiplier and configured to form a second MAC unit with the second CSD multiplier, wherein the re-sampler is configured to generate output samples based on the input samples. A method comprises receiving, by a first CSD multiplier, input samples, receiving, by a second CSD multiplier, the input samples, generating coefficients, scaling, using the first CSD multiplier and the second CSD multiplier, the input samples with coefficient vectors associated with the coefficients to form coefficient vector scaled input samples, and generating output samples based on the coefficient vector scaled input samples. The CSD multipliers may be MC-CSD multipliers.

Abstract: In a described example, a method includes using a power supply, supplying an output voltage that varies in response to a reference voltage; detecting a voltage ramp in an input reference voltage; generating an offset voltage waveform; adding the offset voltage waveform to the input reference voltage to generate a second reference voltage; and using the second reference voltage, operating the power supply to supply the output voltage.

Abstract: In some examples, the disclosure includes a circuit including a power field effect transistor (FET), a gate pull-down circuit, a pull-down bias circuit, and a radio frequency (RF) detector coupled to the source terminal of the power FET and the pull-down bias circuit. In an example, the RF detector circuit is configured to detect a presence of an alternating current signal at a source terminal of the power FET when the power FET is in a non-conductive state and control the pull-down bias circuit to bias the gate pull-down circuit to create a low impedance path between a gate terminal of the power FET and the source terminal of the power FET when the power FET is in the non-conductive state and the alternating current signal is present at the source terminal of the power FET.

Abstract: A self-powered piezoelectric energy harvesting microsystem device has CMOS integrated circuit elements, contacts and interconnections formed at a proof mass portion of a die region of a semiconductor wafer. Piezoelectric energy harvesting unit components connected to the integrated circuit elements are formed at a thinned beam portion of the die region that connects the proof mass portion for vibration relative to a surrounding anchor frame portion. A battery provided on the proof mass portion connects to the integrated circuit elements. In a cantilever architectural example, the battery is advantageously located at a distal end of the proof mass portion, opposite the joinder with frame portion via the beam portion.

Abstract: The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.

Abstract: Touch slider-position sensing useable with a capacitive touch sensor that includes multiple capacitive electrodes arranged to define a slider track. The touch slider-position sensing methodology includes: (a) generating a set of calibration vectors for points of the slider track; (b) determining a touch slider-position based on (i) measuring a measurement/data vector associated with the touch-press slider-location, (ii) determining an angle between the measurement/data vector and a subset of the calibration vectors, and (iii) determining touch slider-position based on the angles between the measurement data vectors and the subset of calibration vectors. The method can include performing a quadratic or higher order interpolation of the angles between the measurement/data vector and the subset of the calibration vectors.

Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.

Abstract: Electronic device manufacturing and configuration methods include performing an additive deposition process that deposits a conductive, resistive, magnetic, semiconductor and/or thermally conductive material over a surface of a processed wafer metallization structure to set or adjust a circuit of a capacitor, an inductor, a resistor, an antenna and/or a thermal component of the metallization structure.

Abstract: A microelectronic device has a pillar connected to an external terminal by an intermetallic joint. Either the pillar or the external terminal, or both, include copper in direct contact with the intermetallic joint. The intermetallic joint includes at least 90 weight percent of at least one copper-tin intermetallic compound. The intermetallic joint is free of voids having a combined volume greater than 10 percent of a volume of the intermetallic joint; and free of a void having a volume greater than 5 percent of the volume of the intermetallic joint. The microelectronic device may be formed using solder which includes at least 93 weight percent tin, 0.5 weight percent to 5.0 weight percent silver, and 0.4 weight percent to 1.0 weight percent copper, to form a solder joint between the pillar and the external terminal, followed by thermal aging to convert the solder joint to the intermetallic joint.

Abstract: A circuit includes a first transistor having a first control input and first and second current terminals, and a second transistor having a second control input and third and fourth current terminals. A third transistor has a third control input and fifth and sixth current terminals, the fifth current terminal coupled to the first current terminal at a first supply voltage node. A fourth transistor has a fourth control input and seventh and eighth current terminals, the seventh current terminal coupled to the second and sixth current terminals. A pulse generator has a pulse generator input and a first pulse generator output, the pulse generator input configured to receive a switch control signal, and the first pulse generator output coupled to the first control input. The third control input is configured to receive either the switch control signal or a logical inverse of the switch control signal.

Abstract: Methods, apparatus, systems, and articles of manufacture to enable status change detection in a low power mode of a microcontroller unit are disclosed herein. An example integrated circuit (IC) includes a controller to determine that the IC is to enter a low power mode. The example IC includes a universal serial bus (USB) physical layer integrated circuit including a transceiver and a detector circuit. The transceiver is disabled while in the low power mode. The detector circuit is enabled while in the low power mode. The detector circuit is to determine whether a pinout of a USB receptacle is shorted to ground. The example IC includes a power control module (PCM) to disable the controller when entering the low power mode. Upon receipt of an indication that the ID pinout of the USB receptacle is shorted to the ground, the PCM initiates a boot sequence.

Abstract: A semiconductor package including a semiconductor die and at least one bondline positioned on the semiconductor die, the at least one bondline comprising a nickel lanthanide alloy diffusion barrier layer abutting a gold layer.

Abstract: An electronic device includes a lead frame, a first clip, a second clip, and a plurality of semiconductor devices. The first clip is stacked with the lead frame. The second clip stacked with the first clip and the lead frame. The second clip includes a first protrusion that engages the first clip and secures the second clip to the first clip. The semiconductor devices are conductively coupled to the lead frame via the first clip and the second clip.

Abstract: A system such as an electric meter includes a single-ended analog-to-digital converter which is susceptible to crosstalk. Methods and apparatus are disclosed to calibrate and cancel crosstalk effects. The system determines whether voltage-induced cross-talk is in-phase or out-of-phase with respect to voltage. The system determines a first calibration factor based on minimum and maximum measured current values and voltage. If the cross-talk is in-phase, the system sets a second calibration factor to 0. If the cross-talk is out-of-phase, the system computes the second calibration factor based on a measured current when a power factor angle is set to 90 degrees. Calibration factors may be stored in the multi-channel system. In use, the system measures current and voltage and computes the actual current, voltage and power based on the measured current and voltage by employing a crosstalk cancellation technique using the calibration factors.

Abstract: An integrated circuit and method with a delamination free opening formed through multiple levels of polymer dielectric. The opening has a vertical sidewall and no interface between adjacent levels of polymer dielectric is exposed on the vertical sidewall.

Abstract: A video hardware engine which support dynamic frame padding is disclosed. The video hardware engine includes an external memory. The external memory stores a reference frame. The reference frame includes a plurality of reference pixels. A motion estimation (ME) engine receives a current LCU (largest coding unit), and defines a search area around the current LCU for motion estimation. The ME engine receives a set of reference pixels corresponding to the current LCU. The set of reference pixels of the plurality of reference pixels are received from the external memory. The ME engine pads a set of duplicate pixels along an edge of the reference frame when a part area of the search area is outside the reference frame.

Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.

Abstract: A system is provided in which a first waveguide has a first resonator coupled to an end of the first waveguide. A second waveguide has a second resonator coupled to the second waveguide. The first resonator is spaced apart from the second resonator by a gap distance. Transmission of a signal propagated by the first waveguide across the gap to the second waveguide is enhanced by a confined near field mode magnetic field produced by the first resonator in response to the propagating wave that is coupled to the second resonator.

Abstract: A motor drive circuit includes a first serializer-deserializer (SER-DES) module that converts first SER-DES input signals into a first SER-DES output serial data stream. The first SER-DES input signals relate to motor control inputs or motor drive power outputs. A second SER-DES module converts a second SER-DES input serial data stream corresponding to the first SER-DES output serial data stream into second SER-DES output signals. The second SER-DES input signals relate to motor drive power outputs or motor control inputs. A serial isolation channel provides a galvanic isolation barrier between the first SER-DES module and the second SER-DES module. The serial isolation channel communicates the first SER-DES output serial data stream across the galvanic isolation barrier to provide the second SER-DES input serial data stream.

Abstract: An example integrated circuit die includes: a plurality of lower level conductor layers, a plurality of lower level insulator layers between the plurality of lower level conductor layers, a plurality of lower level vias extending vertically through the lower level insulator layers, a plurality of upper level conductor layers overlying the lower level conductor layers, a plurality of upper level insulator layers between and surrounding the upper level conductor layers, a plurality of upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.