Abstract: The present disclosure relates to configuring parameters of a system. In some examples, a timer duration circuit can be configured to output a timer duration signal defining a time duration for a retry signal based on an impedance of a first circuit coupled at a first node. A logic circuit can be configured to control an output of the retry signal to at least one integrator circuit to control a current to a second node based on one of the timer duration signal and a retry timer signal, and a combination thereof. An output circuit can be configured to output a stop retry signal based on a voltage established by a second circuit at the second node based on its impedance and the current. The stop retry signal can indicate a number of retries that have occurred and can be based on the capacitances of the first and second circuits.

Abstract: An amplitude limiter circuit includes an inductor and a shunt circuit. The inductor has a first terminal connected to an input node. The shunt circuit is connected to a second terminal of the inductor and also is connected to a low impedance node. If an overvoltage condition forms on the input node, the shunt circuit forms an overvoltage current path from the input node, through the inductor, through the shunt circuit and to low impedance node.

Abstract: In a power converter system, circuitry generates first and second PWM signals during a PWM cycle for controlling application of power to an inductor. Circuitry generates error signals having AC- and DC-components, the error signals being generated in response to indications of the power applied to or developed by the inductor. Circuitry generates a feedback control signal in response to the error signals. The first and second PWM signals are controlled in response to the feedback control signals.

Abstract: A semiconductor package includes a semiconductor die and a ceramic package body covering the semiconductor die. The ceramic package body includes a plurality of contact pads. Each of a first plurality of leads includes a top portion and a bottom portion. The top portion of each of the first plurality of leads is electrically connected to a contact pad of the plurality of contact pads. Each of a second plurality of leads includes a top portion and a bottom portion and an interconnection portion between the top portion and the bottom portion. The top portion of each of the second plurality of leads includes separate finger portions that are electrically connected to at least two of the plurality of contact pads.

Abstract: An interleaved ADC receives an RX signal attenuated by a DSA based on an active DSA setting, within a range of DSA settings (DSA setting range) corresponding to selectable attenuation steps, the DSA setting range partitioned into a number of DSA setting subranges (DSA subranges). The ADC includes an IL mismatch estimation engine in the digital signal path, with an estimation subrange blanker, and an IL mismatch estimator. The estimation subrange blanker is coupled to receive the IADC data stream, and responsive to a DSA subrange allocation signal to select, in each of successive aggregation cycles, IADC data corresponding to an active DSA setting that is within an allocated DSA subrange (DSA active data within an DSA allocated subrange).

Abstract: Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.

Abstract: In a disclosed embodiment, a power line communication (PLC) transmitter includes a forward error correction (FEC) encoder that receives payload data and adds parity information to the data to create an encoded output, a fragmenter that receives the encoded output from the FEC encoder and segments the encoded output into a plurality of fragments, a fragment repetition encoder that receives the plurality of fragments from the fragmenter and copies each of the fragments a selected number of times, and an interleaver that receives the copies of the plurality of fragments from the fragment repetition encoder and interleaves the copies of the plurality of fragments for transmission on a power line.

Abstract: A package for a chip scale atomic clock or magnetometer is disclosed. The package includes a vapor cell using an alkali metal vapor, first and second photodetectors, and a laser operable at a frequency that excites an electron transition in the alkali metal vapor. The laser is positioned to provide an optical signal directed through the vapor cell and towards the first photodetector. The package further contains a polarizing beam splitter, the polarizing beam splitter positioned between the vapor cell and the first photodetector to receive the optical signal and to split the optical signal into a first signal directed toward the first photodetector and a second signal directed toward the second photodetector, the first signal being orthogonal to the second signal.

Abstract: A method for tracking objects in three dimensions in a radar system is provided that includes receiving spherical coordinates of an estimated location of each object of a plurality of detected objects, a range rate of each object, and variances for the spherical coordinates and the range rate of each object, determining whether or not each object is currently being tracked, updating a tracking vector for an object based on the object spherical coordinates, range rate, and variances when the object is currently being tracked, and initializing a tracking vector for an object when the object is not currently being tracked, wherein a tracking vector for an object is a process state vector for an extended Kalman filter designed to track an object, elements of the tracking vector including Cartesian coordinates of the object location, the object velocity in three directions, and the object acceleration in three directions.

Abstract: A reduced pin count (RPC) device includes an electrical circuitry in a package with uniformly distributed leads, a subset of the leads being electrically disconnected form the circuitry. A contactor pin block with sockets corresponding to the uniformly distributed leads has the sockets corresponding to the leads with electrical connections filled with test pins suitable for contacting respective leads, and the sockets corresponding to the electrically disconnected leads voided of test pins. Dummy plugs are inserted into the voided sockets to block the sockets and prevent accidental insertions of test pins.

Abstract: An integrated circuit includes a display sub-system that has a plurality of image processing resources and control logic. The image processing resources include a plurality of image processing pipelines configured to operate in parallel, overlay logic coupled to receive image data from the plurality of image processing pipelines, and an image output port coupled to an output of the overlay logic with image data outputs configured to couple to one or more display devices. The control logic is dynamically configurable to assign each of the image processing resources to a selected one of a first control port and a second control port. The first control port is configured to be controlled exclusively by a first processor and the second control port is configured to be controlled exclusively by a second processor.

Abstract: An apparatus for a beam steering device includes a rotator constituting a cylindrical body extending along an axis and defining a central passage therethrough. A wedge-shaped prism is secured to the body within the central passage. The prism has a first surface extending perpendicular to the axis and a second surface extending transverse to the axis. A drive member is provided on one of an axial end surface and a radially outer surface of the body for rotating the rotator. An encoder member is provided on the same surface of the body as the drive member for tracking the position of the rotator.

Abstract: For producing a low-power, low-phase noise oscillating signal using a self-injection locking oscillator, examples include: producing, using an oscillator, a signal having a base frequency component and an Nth harmonic component, in which N is a selected integer and N>1; filtering the signal through a bandpass filter with Q factor ?5, the filter configured to pass the Nth harmonic component as a filtered Nth harmonic component; and injecting the filtered Nth harmonic component into the oscillator to self-injection lock the base frequency of the signal.

Abstract: A method of image processing in a structured light imaging device is provided that includes receiving a captured image of a scene, wherein the captured image is captured by a camera of a projector-camera pair in the structured light imaging system, and wherein the captured image includes a pre-determined hierarchical binary pattern projected into the scene by the projector, wherein the pre-determined hierarchical binary pattern was formed by iteratively scaling a lower resolution binary pattern to multiple successively higher resolutions, rectifying the captured image to generated a rectified captured image, extracting a binary image from the rectified captured image at full resolution and at each resolution used to generate the pre-determined hierarchical binary pattern, and using the binary images to generate a depth map of the captured image.

Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.

Abstract: In described examples, a stochastic comparator includes a first comparator that compares an input signal and a primary threshold to generate a first signal. A second comparator compares the input signal and the primary threshold to generate a second signal. A decision block generates a control signal in response to the first signal, the second signal and a PRBS (pseudo random binary sequence) signal. A XOR gate generates a detection signal in response the first signal and the second signal.

Abstract: A plasma processing tool for fabricating a semiconductor device on a semiconductor wafer includes an optical window disposed on a plasma chamber, remotely from a plasma region. The window is thermally connected to an electrical heater element capable of maintaining the window at a temperature of at least 30° C. A heater controller provides electrical power to the heater element. During operation of the plasma processing tool, the heater controller provides power to the heater element so as to maintain the window at a temperature of at least 30° C. during at least a portion of a plasma process step in which by-products are produced in the plasma chamber.

Abstract: The disclosure provides a flip-flop. The flip-flop includes a master latch. The master latch receives a flip-flop input, a clock input, an inverted clock input, an enable signal and an inverted enable signal. A slave latch is coupled to the master latch and receives the enable signal and the inverted enable signal. An output inverter is coupled to the slave latch and generates a flip-flop output.

Abstract: An integrated circuit is provided with a voltage sag detector (VSD) within the integrated circuit package. The VSD is coupled to a voltage reference and to the power distribution bus within the integrated circuit. The VSD has an output for indicating when a voltage level on the power distribution bus sags below a voltage level provided by the voltage reference.

Abstract: An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.