Abstract: Disclosed examples provide processes for fabricating a semiconductor product and for forming a patterned stack with an aluminum layer and a tungsten layer, including forming a first dielectric layer on a gate structure and on first and second regions of a substrate, forming a diffusion barrier layer on the first dielectric layer, forming a tungsten layer on the diffusion barrier layer, forming an aluminum layer on the tungsten layer, forming a hard mask on the aluminum layer, forming a patterned resist mask which covers the hard mask above the first region and exposes the hard mask layer above the second region, dry etching the hard mask and the aluminum layer above the second region using the patterned resist mask layer, removing the resist mask, and dry etching the tungsten layer using the hard mask layer to expose the first dielectric layer above the second region.

Abstract: A reference signal generator includes a voltage reference, an amplifier coupled to the voltage reference, and a precharge circuit coupled to the amplifier. The voltage reference is configured to generate a constant voltage. The amplifier is configured to receive the constant voltage from the voltage reference and generate a regulating primary output signal and a non-regulating secondary output signal. The precharge circuit is configured to charge a noise reduction capacitor with the non-regulating secondary output signal.

Abstract: A passive beamformer for ultrasound imaging. An ultrasound probe includes a plurality of ultrasound transducers and beamforming circuitry. Each of the ultrasound transducers is configured to convert ultrasonic signal into electrical signal. The beamforming circuitry is coupled to the plurality of ultrasound transducers. The beamforming circuitry includes a plurality of passive delay circuits and a passive hold circuit. One of the passive delay circuits is coupled to each of the ultrasound transducers. The passive hold circuit is coupled to the passive delay circuits to store a sum of the charges received from the delay circuits.

Abstract: A method and circuitry that enables an input/output pin (I/O) on a System on a Chip to function either as an analog or as a digital input/output without compromising the overall performance of the system, thus giving the automated test equipment full flexibility to maximize parallel testing for both analog and digital modules.

Abstract: An integrated circuit (“IC”) package mold includes an upper mold platen that defines an upper mold cavity for receiving an upper substrate having a die attach side with a plurality of dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the upper substrate faces upwardly. A lower mold platen defines a lower mold cavity for receiving a lower substrate having a die attach side with a plurality dies mounted thereon and a non-attach side with no dies mounted thereon. The die attach side of the lower substrate faces downwardly.

Abstract: In a described example, a method for making a packaged semiconductor device includes laser ablating a first groove with a first width and a first depth into a mounting surface of a substrate between landing pads. A first pillar bump on an active surface of a semiconductor device is bonded to a first landing pad; and a second pillar bump on the semiconductor device is bonded to a second landing pad. A channel forms with the active surface of the semiconductor device forming a first wall of the channel, the first pillar bump forms a second wall of the channel, the second pillar bump forming a third wall of the channel, and a surface of the first groove forms a fourth wall of the channel. The channel is filled with mold compound and at least a portion of the substrate and the semiconductor device are covered with mold compound.

Abstract: In at least some embodiments, a system comprises a frequency generator configured to generate a second clock signal having a second frequency using a first clock signal having a first frequency. The second frequency is offset from the first frequency and each of a plurality of harmonic frequencies of the second frequency is offset from a harmonic frequency of the first frequency. The system also includes a power converter configured to produce a power signal that at least partially corresponds to the second frequency. The system further comprises an analog-to-digital converter (ADC) configured to sample and convert analog voltages at the first frequency. The ADC is powered by the power signal.

Abstract: Described examples include a substrate made of a first material and having a surface. First and second nozzles respectively dispense a first solvent paste including electrically conductive nanoparticles and a second solvent paste including non-conductive nanoparticles, while moving over the surface of the substrate. The first and second nozzles additively deposit a uniform layer including sequential and contiguous zones, alternating between the first solvent paste and the second solvent paste. Energy is applied to sinter together the nanoparticles and diffuse the nanoparticles into the substrate. The sintered nanoparticles form a layer composed of an alternating sequence of electrically conductive zones contiguous with electrically non-conductive zones.

Abstract: Methods, apparatus, systems, and articles of manufacture for zero voltage switching of flyback converters are disclosed. An example apparatus includes a first driver to operate a first switch to direct a first current to flow to a first winding of a transformer, and a second driver to operate a second switch to direct a second current to flow to a second winding of the transformer and operate the second switch to cause the second current to discharge a voltage of the first switch.

Abstract: A power supply module includes a metallic clip including a plate having an area and a first and a second ridge on opposite sides of the plate. The ridges bent in the same direction away from the plate. The first and the second ridges conductively attached to the substrate, where the substrate is of insulating material integral with metal traces, the plate roofing over the substrate between the ridges. A first MOS field-effect transistor (FET) chip and, horizontally side-by-side, a second MOSFET chip are attached and wire bonded to the substrate under the plate. The drain of the first MOSFET is connected to the input terminal of the module, the source of the first MOSFET is tied to the drain of the second MOSFET, and the source of the second MOSFET, together with the second ridge, is connected to ground. A driver and controller chip is attached to the substrate under the plate and wire bonded to the gates of the first and second MOSFET.

Abstract: In at least some embodiments, a system comprises a socket gate terminal configured to receive a first voltage to activate and inactivate a device under test (DUT) coupled to the socket gate terminal. The system also comprises a socket source terminal configured to provide a reference voltage to the DUT. The system further comprises a socket drain terminal configured to provide a second voltage to the DUT to stress the DUT when the DUT is inactive. The socket drain terminal is further configured to receive a third voltage to cause a current to flow through a pathway in the DUT between the socket drain terminal and the socket source terminal when the DUT is active. The socket drain terminal is further configured to provide a fourth voltage indicative of a resistance of the pathway in the DUT when the DUT is active and is heated to a temperature above an ambient temperature associated with the system.

Abstract: A method to fabricate a transistor comprises: forming a first dielectric layer on a semiconductor substrate; depositing a barrier layer on the first dielectric layer; depositing an anti-reflective coating on the barrier layer; depositing and exposing a pattern in a photoresist layer to radiation followed by etching to provide an opening; etching a portion of the anti-reflective coating below the opening; etching a portion of the barrier layer below the opening to expose a portion of the first dielectric layer; providing an ambient oxidizing agent to grow an oxide region followed by removing the barrier layer; implanting dopants into the semiconductor substrate after removing the barrier layer; removing the first dielectric layer after implanting dopants into the semiconductor substrate; and forming a second dielectric layer after removing the first dielectric layer, wherein the oxide region is grown to be thicker than the second dielectric layer.

Abstract: A delta-sigma modulator architecture with idle tone suppression based on injecting an out-of-band signal includes: modulator input circuitry to provide a modulator input signal; modulator loop circuitry to quantize the modulator input signal to generate a modulator output signal at an oversampling frequency, and to provide a feedback signal. Digital filtering circuitry filters the modulator output signal to provide a digital output signal at a data rate frequency related to the oversampling frequency by a defined oversampling ratio. Out-of-band (OoB) signal generator circuitry injects a deterministic OoB injection signal at a defined OoB frequency outside of a target frequency band. The modulator input circuitry combines the analog input signal, the feedback signal, and the OoB injection signal into the modulator input signal. The digital filtering circuitry filters the OoB injection signal. The OoB injection signal can be selectively defined to suppress idle tones generated in the modulator loop circuitry.

Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.

Abstract: In described examples, a time-domain analyzer is arranged to generate an indication of a number of high-frequency events of an electrical monitor signal that includes a fundamental periodic frequency. The high-frequency events include frequencies higher than the fundamental periodic frequency. A frequency-domain analyzer is arranged to generate frequency band information in response to frequencies of the electrical monitor signal that are higher than the fundamental periodic frequency. A fault detector is arranged to monitor the indication of the number of high-frequency events and the generated frequency band information, and to generate a fault flag in response to the monitored indication of the number of high-frequency events and the generated frequency band information.

Abstract: An electronic circuit (200) includes one or more programmable control-plane engines (410, 460) operable to process packet header information and form at least one command, one or more programmable data-plane engines (310, 320, 370) selectively operable for at least one of a plurality of cryptographic processes selectable in response to the at least one command, and a programmable host processor (100) coupled to such a data-plane engine (310) and such a control-plane engine (410). Other processors, circuits, devices and systems and processes for their operation and manufacture are disclosed.

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

Abstract: An electronic circuit (4000) includes a bias value generator circuit (3900) operable to supply a varying bias value in a programmable range, and an instruction circuit (3625, 4010) responsive to a first instruction to program the range of the bias value generator circuit (3900) and further responsive to a second instruction having an operand to repeatedly issue the second instruction with the operand varied in an operand value range determined as a function of the varying bias value.

Abstract: Performing series equivalent scans spanning a plurality of scan technologies in a complex scan topology may be performed by performing shift operations in the complex scan topology while only one branch of the complex scan topology connectivity is enabled, and performing capture and update operations in parallel while scan topology connectivity of two or more of the plurality of scan technologies is enabled.