Patents Assigned to Texas Instruments
  • Unguarded schottky barrier diodes
    Patent number: 10535783
    Abstract: One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric interface surface that laterally extends around a perimeter of the recessed region. The diode further includes an anode that conforms to the recessed region. A dielectric layer extends over the dielectric interface surface of the cathode and further extends over a portion of the anode near the perimeter. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: January 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Vladimir Frank Drobny
  • Capacitive touch sensor and method
    Patent number: 10534491
    Abstract: A capacitive touch sensor is disclosed for use with input signal. The capacitive touch sensor includes a number n of input/output lines. Each of the number n of input/output lines is electrically disconnected from every other of the number n of input/output lines. Each of the number n of input/output lines is arranged to cross every other of the number n of input/output lines. Each of a number ? of positions, includes one of the number n of input/output lines crossing another of the number n of input/output lines.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhang Jun, Shen Ge, Xu Kang Cheng, Zhou Yi, Hao Meng, Ji Ru Jun
  • Wire support for a leadframe
    Patent number: 10529654
    Abstract: A leadframe includes a plurality of interconnected support members. A pair of die pads is connected to the support members and configured to receive a pair of dies electrically connected by at least one wire. A support bracket extends between the die pads and includes a surface for maintaining the at least one wire at a predetermined distance from the die pads during overmolding of the leadframe.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yuh-Harng Chien, Chih-Chien Ho, Steven Su
  • Wideband low distortion power amplifier
    Patent number: 10530402
    Abstract: A circuit and apparatus for filtering harmful harmonics is disclosed. The circuit and apparatus include a power amplifier core that uses equally sized inverter based amplifiers. The amplifier core cells provide uniform load to all phases of a fundamental frequency to cancel all harmonics at an output. The power amplifier stages are driven into nonlinearity, and the combination of harmonics is performed at the output by varying series connected capacitors. The harmonic combination is performed at the outputs, leaving no further scope of nonlinearity in the signal chain.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sudipto Chakraborty
  • Butterfly network on load data return
    Patent number: 10530397
    Abstract: A method is shown that is operable to transform and align a plurality of fields from an input to an output data stream using a multilayer butterfly or inverse butterfly network. Many transformations are possible with such a network which may include separate control of each multiplexer. This invention supports a limited set of multiplexer control signals, which enables a similarly limited set of data transformations. This limited capability is offset by the reduced complexity of the multiplexor control circuits.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Dheera Balasubramanian, Joseph Zbiciak, Duc Quang Bui, Timothy David Anderson
  • Conductivity modulated drain extended MOSFET
    Patent number: 10529708
    Abstract: An integrated circuit is fabricated on a semiconductor substrate. An insulated gate bipolar transistor (IGBT) is formed upon the semiconductor substrate in which the IGBT has an anode terminal, a cathode terminal, and a gate terminal, and a drift region. A diode is also formed on the semiconductor substrate and has an anode terminal and a cathode terminal, in which the anode of the diode is coupled to the anode terminal of the IGBT and the cathode of the diode is coupled to the drift region of the IGBT.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Aravind C Appaswamy, James P. Di Sarro, Farzan Farbiz
  • System of power-saving in MEMS sensor applications
    Patent number: 10527453
    Abstract: A system comprises a plurality of sensors, a sensor processor, and a sampling rate engine. The sensor processor is coupled to an output of each sensor of the plurality of sensors. The sensor processor estimates user dynamics in response to a first output signal of a first sensor of the plurality of sensors. The sampling rate engine is coupled to an output of the sensor processor. The sampling rate engine determines a sampling rate value of a second sensor of the plurality of sensors in response to a user dynamics value from the sensor processor. The second sensor comprises a selectable sampling rate. The selectable sampling rate is configured in response to the sampling rate value determined by the sampling rate engine.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Deric Wayne Waters, Jayawardan Janardhanan, Saket Thukral
  • Integrated circuit nanoparticle thermal routing structure over interconnect region
    Patent number: 10529641
    Abstract: An integrated circuit has a thermal routing structure above a top interconnect level. The top interconnect level includes interconnects connected to lower interconnect levels, and does not include bond pads, probe pads, input/output pads, or a redistribution layer to bump bond pads. The thermal routing structure extends over a portion, but not all, of a plane of the integrated circuit containing the top interconnect level. The thermal routing structure includes a layer of nanoparticles in which adjacent nanoparticles are attached to each other. The layer of nanoparticles is free of an organic binder material. The thermal routing structure has a thermal conductivity higher than the metal in the top interconnect level. The layer of nanoparticles is formed by an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Multi-phase multi-frequency pulse width modulation
    Patent number: 10530344
    Abstract: In described examples, a method of generating a pulse width modulation (PWM) signal includes repeatedly master control counting, by a master control counter generator, which includes one or both of incrementing and decrementing a master control counter with a minimum value and a maximum value, and repeatedly slave control counting with a phase delay with respect to the master control counting, and during a transition period, slave control counting to a new maximum value or a new phase delay. A maximum count of the transition period is selected to result in the transition period reaching the minimum value at the new phase delay count. The PWM signal is generated by generating rising edges when the slave control counter reaches a rising edge threshold, and generating falling edges when the slave control counter reaches a falling edge threshold.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hrishikesh Ratnakar Nene, Subrahmanya Bharathi Akondy, Kristopher Sean Parrent
  • Method of fabricating non-etch gas cooled epitaxial stack for group IIIA-N devices
    Patent number: 10529561
    Abstract: A method of fabricating an epitaxial stack for Group IIIA-N transistors includes depositing at least one Group IIIA-N buffer layer on a substrate in a deposition chamber of a deposition system. At least one Group IIIA-N cap layer is then deposited on the first Group IIIA-N buffer layer. During a cool down from the deposition temperature for the cap layer deposition the gas mixture supplied to the deposition chamber includes NH3 and at least one other gas, wherein the gas mixture provide an ambient in the deposition chamber that is non-etching with respect to the cap layer so that at a surface of the cap layer there is (i) a root mean square (rms) roughness of <10 ? and (ii) a pit density for pits greater than (>) 2 nm deep less than (<) 10 pits per square ?m with an average pit diameter less than (<) 0.05 ?m.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Asad Mahmood Haider, Qhalid Fareed
  • Galvanic isolation device
    Patent number: 10529796
    Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Barry Jon Male, Robert Alan Neidorff
  • Method and circuitry for on-chip electro-static discharge protection scheme for low cost gate driver integrated circuit
    Patent number: 10529702
    Abstract: An apparatus includes an integrated circuit, a plurality of bi-directional pins, and an electro-static discharge (ESD) clamp. The integrated circuit is configured to provide a ground potential. The plurality of bi-directional pins are configured to provide a differential input signal for the integrated circuit. The electro-static discharge (ESD) clamp is coupled between the ground potential and the plurality of bi-directional pins.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zhong Chen, Danyang Zhu, Zhuang Ma
  • Sample based gain error estimation for analog to digital converter
    Patent number: 10530378
    Abstract: The disclosure provides a circuit. The circuit includes a zone detection block that generates a control signal in response to an input signal. An amplifier generates an amplified signal in response to the input signal and the control signal. An analog to digital converter (ADC) is coupled to the amplifier and samples the amplified signal to generate a digital signal. A digital corrector is coupled to the zone detection block and the ADC, and transforms the digital signal to generate a rectified signal based on the control signal and an error signal. An error estimator is coupled to the zone detection block and receives the rectified signal as a feedback. The error estimator generates the error signal in response to the control signal and the rectified signal.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivas Kumar Reddy Naru, Nagarajan Viswanathan, Visvesvaraya Pentakota
  • Integrated circuit, LDMOS with trapezoid JFET, bottom gate and ballast drift and fabrication method
    Patent number: 10529804
    Abstract: Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jun Cai
  • Integrated transistor and protection diode and fabrication method
    Patent number: 10529705
    Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.
    Type: Grant
    Filed: April 1, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Baiocchi
  • Offset drift compensation
    Patent number: 10530308
    Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shyamsunder Balasubramanian, Wenxiao Tan, Mayank Garg, Toru Tanaka
  • Current mode chopper amplifier
    Patent number: 10530302
    Abstract: A circuit, comprising an input chopper configured to receive an input signal, a differential amplifier having an input coupled to an output of the input chopper, a current mode chopping circuit coupled to an output of the differential amplifier, and a first current mirror bias transistor pair coupled between a voltage supply and the current mode chopping circuit.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ravinthiran Balasingam, Dimitar Trifonov, Biraja Prasad Dash
  • Integrated transistor and protection diode and fabrication method
    Patent number: 10529706
    Abstract: Disclosed examples provide integrated circuits including a source down transistor with a gate, a body region, an n-type source region, an n-type drain region, a p-type body contact region below the n-type source region which extends to a first depth, along with a protection diode which includes an n-type cathode region, and a p-type anode region below the n-type cathode region, where the breakdown voltage of the protection diode is defined by adjusting the relative doping concentrations and/or the vertical locations of the p-type anode region with respect to the n-type cathode region.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Haian Lin, Frank Baiocchi
  • Methods and apparatus for LIDAR with DMD
    Patent number: 10527726
    Abstract: In described examples, a system for outputting a patterned light beam includes a digital micro-mirror device having an array of micro-mirrors. Diffraction patterns displayed using the digital micro-mirror device create at least one patterned light beam in a field of view. An illumination source illuminates the array of micro-mirrors in the digital micro-mirror device. The system includes a processor coupled to provide display diffraction patterns for display using the digital micro-mirror device and to control the illumination source, and at least one detector to detect light from the patterned light beam that reflects from objects in the field of view.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Terry Alan Bartlett, Stephen Aldridge Shaw, Patrick Ian Oden
  • Infrared sensor design using an epoxy film as an infrared absorption layer
    Patent number: 10526198
    Abstract: A MEMS IR sensor, with a cavity in a substrate underlapping an overlying layer and a temperature sensing component disposed in the overlying layer over the cavity, may be formed by forming an IR-absorbing sealing layer on the overlying layer so as to cover access holes to the cavity. The sealing layer is may include a photosensitive material, and the sealing layer may be patterned using a photolithographic process to form an IR-absorbing seal. Alternately, the sealing layer may be patterned using a mask and etch process to form the IR-absorbing seal.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 7, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ricky Alan Jackson, Walter Baker Meinel, Kalin Valeriev Lazarov, Brian E. Goodlin