Abstract: A method and apparatus for fast charging a battery with optimal charging. In an arrangement, a system includes a battery charger for applying a voltage to a rechargeable battery; and a controller coupled to the battery charger and monitoring at least one of a battery voltage, a battery temperature, and the current flowing into the battery; wherein the system is configured to apply a charging current from the battery charger by calculating an open cell anode voltage and an anode resistance of the battery, and determining the charging current. In additional arrangements, lithium ion plating is prevented by the charging current. Additional methods and arrangements are disclosed.

Abstract: Control circuits and methods to operate a switch of a DC-DC converter, including an output circuit to turn the switch off to control a peak inductor current in a given switching control cycle, and a modulation circuit to implement transition mode (TM) or continuous conduction mode (CCM) operation for a given switching control cycle by causing the output circuit to turn the switch on in response to an earlier one of a first signal, that represents an inductor current of the DC-DC converter, decreasing to a reference voltage that represents a zero crossing of the inductor current for the TM operation or the first signal decreasing to a valley reference signal that represents a non-zero value of the inductor current for the CCM operation.

Abstract: In a described example, an integrated circuit (IC) package includes: an IC chip bonded to a chip mount pad on a lead frame; low modulus molding compound surrounding the IC chip; and IC package molding compound covering the IC chip, and at least a portion of the low modulus molding compound.

Abstract: A photovoltaic system with an inverter, at least one solar panel for providing electrical power, and electrical wiring for coupling electrical power from the at least one solar panel to the inverter. Also included is a transmitter for transmitting a messaging protocol along the electrical wiring, where the protocol includes a multibit wireline signal. Also included is circuitry for selectively connecting the electrical power from the at least one solar panel along the electrical wiring to the inverter in response to the messaging protocol.

Abstract: A wireless communication receiver including a serial to parallel converter receiving an radio frequency signal, a fast Fourier transform device connected to said serial to parallel converter converting NFFT corresponding serial signals into a frequency domain; an EZC root sequence unit generating a set of root sequence signals; an element-by-element multiply unit forming a set of products including a product of each of said frequency domain signals from said fast Fourier transform device and a corresponding root sequence signal, an NSRS-length IDFT unit performing a group cyclic-shift de-multiplexing of the products and a discrete Fourier transform unit converting connected cyclic shift de-multiplexing signals back to frequency-domain.

Abstract: A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

Abstract: A class AB amplifier with improved DC gain. An amplifier includes an input stage and an output stage. The output stage is configured to amplify an output of the input stage. The output stage includes output transistors, class AB amplifier circuitry, minimum selector circuitry, and gain boost amplifier circuitry. The class AB amplifier circuitry includes a first transistor and a second transistor connected as a differential amplifier. The minimum selector circuitry is configured to control bias current in the output transistors by driving a control input of the first transistor. The gain boost amplifier circuitry is coupled to the class AB amplifier circuitry. The gain boost amplifier circuitry is configured to drive a common mode signal onto the control input of the first transistor and a control input of the second transistor, the common mode signal based on the output of the input stage.

Abstract: A hot swap controller circuit includes a comparator and current control circuitry. The comparator is configured to compare voltage across a power transistor controlled by the hot swap controller circuit to a predetermined threshold voltage. The current control circuitry is coupled to the comparator. The current control circuitry is configured to limit current through the power transistor to no higher than a predetermined high current based on the voltage across the transistor being less than the predetermined threshold voltage. The current control circuitry is also configured to limit the current through the transistor to be no higher than a predetermined low current based on the voltage across the transistor being greater than the predetermined threshold voltage. The predetermined high current is greater than the predetermined low current.

Abstract: An optocoupler is placed in series between the field ground pin of digital input circuitry and the field ground of an industrial controller. A capacitor to field ground is provided for each digital input. A resistor is provided to the input pin of the digital input circuitry. To detect a broken wire a test pulse is provided to the optocoupler connected in the ground path. This test pulse isolates the digital input circuitry from field ground. As current is always being provided from the field when the wire is not broken, the capacitor connected between the input and ground charges. After the test pulse has completed, the output signal of the digital input circuitry is examined. If the level indicates the input is high, the wire is not broken. If, however, the output remains low indicating that the input is low, the wire has broken.

Abstract: A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.

Abstract: A p-type metal oxide semiconductor field effect transistor (PFET) includes a p-type silicon substrate and an n-type well formed in the p-type silicon substrate. The PFET also comprises a p-type source formed in the n-type well, a p-type drain formed in the n-type well, and dual pockets implanted in the n-type well and coupled to the source and drain. The dual pockets comprise a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants.

Abstract: In examples, a system comprises a differential amplifier coupled to a parasitic capacitor positioned between a first node and a first reference voltage source. The system comprises a buffer amplifier having an input terminal and an output terminal, the input terminal coupled to the first node and the output terminal coupled to a cancellation capacitor. The system includes a controlled current source coupled to the first node and the input terminal, the controlled current source coupled to a second reference voltage source. The system comprises a current sense circuit coupled to the cancellation capacitor and the second reference voltage source.

Abstract: A circuit for a multi-phase power regulator including a power stage with a first phase and a second phase, the circuit including phase management circuitry coupled to the first phase and the second phase to control the first phase and the second phase, a first comparator coupled to an output of the multi-phase power regulator to compare a value of the output of the multi-phase power regulator to a first threshold value to produce a first comparison result, and phase shedding circuitry coupled to the first comparator and the phase management circuitry to control the phase management circuitry to activate or deactivate the second phase based at least partially on the first comparison result.

Abstract: A flexible hybrid firewall architecture that allows a mix of firewalls at end points in front of a target and at the initiator points. Groups of Priv-IDs may be created where each group is isolated from other worlds, with all firewalls controlled by a device management and security module.

Abstract: A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

Abstract: A packaged semiconductor device includes a leadframe (LF) having a plurality of laminate-supporting pedestals. A cured first die attach (DA) material is on an outer edge of the pedestals being an ultraviolet (UV)-curing DA material having a photoinitiator or a cured B-stage DA material. A cured thermally-curing DA material is on an area of the pedestals not occupied by the UV-curing DA material. A laminate component having bond pads on a top side is mounted top side up on the plurality of pedestals.

Abstract: Methods, apparatus, systems to perform distance-based feature suppression of features of an image in a feature list of the image are disclosed. A method includes accessing the feature list, comparing a selected feature in the feature list with features located within a first distance of the selected feature, when features located within the first distance are non-suppressed or valid and are stronger than different non-suppressed features, marking the features as valid and marking other non-suppressed features as suppressed. When the features are suppressed or invalid and are not stronger than non-suppressed features, determining if features of the feature list are marked as valid or suppressed.

Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: An integrated circuit includes phase locked loop (PLL) circuitry, voltage controlled oscillator (VCO) circuitry, and interface circuitry. The PLL circuitry includes a reference signal input terminal, a reference frequency divider circuit, a reference signal output terminal, a switch, a phase detector, a charge pump, and a control voltage output terminal. The reference frequency divider circuit is coupled to the reference signal input terminal. The switch is coupled to the reference frequency divider circuit and to the reference signal output terminal. The switch is configured to switchably connect the reference frequency divider circuit to the reference signal output terminal. The VCO circuitry includes a control voltage input terminal, a VCO, calibration circuitry, and a calibration input/output (I/O) terminal. The VCO is coupled to the control voltage input terminal. The calibration circuitry is coupled to the VCO. The calibration I/O terminal is coupled to the calibration circuitry.