Abstract: Systems and methods for wireless power transfer with fractional timing resolution are described. In some embodiments, an electrical power transmitter may include a transistor and a rising edge control circuit configured to control a gate of the transistor to produce a rising edge of a pulse at a time selected with a resolution greater than a full-clock period.

Abstract: An integrated circuit (IC) includes a first field-plated field effect transistor (FET), and a second field-plated FET, and functional circuitry configured together with the field-plated FETs for realizing at least one circuit function in a semiconductor surface layer on a substrate. The field-plated FETs include a gate structure including a gate electrode partially over a LOCOS field relief oxide and partially over a gate dielectric layer. The LOCOS field relief oxide thickness for the first field-plated FET is thicker than the LOCOS field relief oxide thickness for the second field-plated FET. There are sources and drains on respective sides of the gate structures in the semiconductor surface layer.

Abstract: A forward-backward Kalman filter for estimating phase noise present in a received signal. Both the forward and backward Kalman filters use hard-decision measurements of the received symbols. The phase noise estimate from the forward Kalman filter is used as a coarse phase noise estimate for the backward Kalman filter and vice versa. The final phase noise estimate is an optimal combination of the forward phase noise estimate and backward phase noise estimate.

Abstract: A method for encoding a video sequence in a scalable video encoder to generate a scalable bitstream is provided that includes encoding the video sequence in a first layer encoder of the scalable video encoder to generate a first sub-bitstream, encoding the video sequence in a second layer encoder of the scalable video encoder to generate a second sub-bitstream, wherein portions of the video sequence being encoded in the second layer encoder are predicted using reference portions of the video sequence encoded in the first layer encoder, combining the first sub-bitstream and the second sub-bitstream to generate the scalable bitstream, and signaling in the scalable bitstream an indication of a maximum decoded picture buffer (DPB) size needed for decoding the second sub-bitstream and the first sub-bitstream when the second sub-bitstream is a target sub-bitstream for decoding.

Abstract: In an example, an integrated circuit includes a communication and control unit. The communication and control unit controls an inverter that applies an alternating current output signal to a transmission coil for reception by a receiver. The communication and control unit causes the inverter to provide a first and second transmit powers to the transmission coil, and the communication unit receives a first and second power received signals from the receiver in response to the first and second transmit powers. The communication and control unit determines a first gain and offset using the first transmit power, the first power. When a third transmit power greater than the second transmit power is transmitted by the transmission coil, the communication and control unit determines a second gain and a second offset using the first transmit power, the first power received signal, the third transmit power and a third power received signal.

Abstract: Transmitter circuitry transmits: a first voltage as the return-to-zero signal that is higher than a first positive threshold, the first voltage being decodable to a first order of data bits; a second voltage as a return-to-zero signal that is between a second positive threshold and the first positive threshold, the second voltage being decodable to a second order of the data bits, and the second positive threshold being lower than the first positive threshold; a third voltage as the return-to-zero signal that is between a first negative threshold and a second negative threshold, the third voltage being decodable to a third order of the data bits, and the second negative threshold being higher than the first negative threshold; and a fourth voltage as the return-to-zero signal that is lower than the first negative threshold, the fourth voltage being decodable to a fourth order of the data bits.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which an oxide structure is formed over a drift region of a semiconductor substrate, and a shallow implantation process is performed using a first mask that exposes the oxide structure and a first portion of the semiconductor substrate to form a first drift region portion for connection to a body implant region. A second drift region portion is implanted in the semiconductor substrate under the oxide structure by a second implantation process using the first mask at a higher implant energy.

Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods in which a silicide block material or other protection layer is formed on a field oxide structure above a drift region to protect the field oxide structure from damage during deglaze processing. Further described examples include a shallow trench isolation (STI) structure that laterally surrounds an active region of a semiconductor substrate, where the STI structure is laterally spaced from the oxide structure, and is formed under gate contacts of the transistor.

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

Abstract: A method of forming an electronic device includes forming first, second and third doped regions at a surface of a semiconductor substrate. A first buried layer is located within the semiconductor substrate below the first, second and third doped regions. Fourth and fifth doped regions are laterally spaced apart along the substrate and extend from the surface of the substrate to the first buried layer, the first, second and third doped regions being located between the fourth and fifth doped regions. A second buried layer is formed within the substrate and between the fourth and fifth doped regions such that a first portion of the semiconductor substrate is located between the first buried layer and the second buried layer, and a second portion of the semiconductor substrate is located between the first, second and third doped regions and the second buried layer.

Abstract: A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.

Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.

Abstract: Described herein is a technology for implementing a decoupling circuit (104) to increase reliability of a DC-DC power converter (100). To absorb an overshoot transient voltage, the decoupling circuit includes a first capacitor (214) and a second capacitor (216) that charge energy during a short burst of upward electrical energy. During an undershoot transient voltage, however, the first capacitor and second capacitor discharge energy to a transistor (108). In certain embodiment, such as the transistor that requires higher voltage switching, the decoupling circuit is connected in series with another decoupling circuit.

Abstract: A resonant line driver for driving capacitive-loads includes a driver series-coupled to an energy transfer inductor L1, driving signal energy at a signal frequency through L1. A switch array is controlled to switch L1 between multiple electrodes according to a switching sequence, each electrode characterized by a load capacitance CL. L1 and CL form a resonator circuit in which signal energy cycles between L1 and CL at the signal frequency. The switch array switches L1 between a current electrode and a next electrode at a zero_crossing when signal energy in the energy transfer inductor is at a maximum and signal energy in the load capacitance of the current electrode is at a minimum. An amplitude control loop controls signal energy delivered to the L1CL resonator circuit, and a frequency control loop controls signal frequency/phase. In an example application, the resonant driver provides line drive for a mutual capacitance touch screen.

Abstract: One example is a system for controlling a motor during startup. The system includes measurement logic, pattern detection logic, and mode logic. The measurement logic monitors a back-electromotive force (BEMF) signal representing a BEMF of an electric motor and the pattern detection logic monitors this signal to detect instances of the monitored BEMF signal exhibiting a predetermined pattern. The mode logic enables control of the electric motor according to a plurality of modes of control. In some examples, the mode logic initially employs a first mode of control and switches from the first mode of control to a second mode of control in response to the pattern detection logic detecting that a BEMF signal exhibits the predetermined pattern over a plurality of commutation states.

Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.

Abstract: Disclosed examples include digital isolator modules, isolation circuitry and low-loss multi-order bandpass filter circuits, including a capacitive coupled galvanic isolation circuit with first and second coupling capacitors individually including a first plate and a second plate, and a bond wire connecting the first plates of the coupling capacitors, a first circuit with a first inductor coupled to form a first resonant tank circuit with a first parasitic capacitor associated with the second plate of the first coupling capacitor, and a second circuit with a second inductor coupled to form a second resonant tank circuit with a second parasitic capacitor associated with the second plate of the second coupling capacitor.

Abstract: A method for displaying a surround view on a single display screen is disclosed. A plurality of image frames for a particular time may be received from a corresponding plurality of cameras. A viewpoint warp map corresponding to a predetermined first virtual viewpoint may be selected, wherein the viewpoint warp map defines a source pixel location in the plurality of image frames for each output pixel location in the display screen. The warp map was predetermined offline and stored for later use. An output image is synthesized for the display screen by selecting pixel data for each pixel of the output image from the plurality of image frames in accordance with the viewpoint warp map. The synthesized image is then displayed on a display screen.

Abstract: Regulating voltages at inputs of an electronic device by performing at least the following: receiving, at a voltage monitoring circuit, a monitoring voltage corresponding to a power system, determining, at the voltage monitoring circuit, whether the monitoring voltage is equal to or exceeds a monitoring threshold voltage, receiving, at the voltage monitoring circuit, an output indicating whether an inputted reference voltage and an inputted feedback voltage at a comparator circuit differs, regulating, at the voltage monitoring circuit, a feedback voltage to match the inputted reference voltage based on the output and a determination that the monitoring voltage is equal to or exceeds the monitoring threshold voltage, and providing, from the voltage monitoring circuit, the feedback voltage as an updated inputted feedback voltage for the comparator circuit.

Abstract: One example includes a light-emitting diode (LED) system. The LED system includes an LED array comprising a plurality of LEDs that are each activated via an LED current provided therethrough to provide illumination. The system also includes an LED controller configured to sequentially activate the plurality of LEDs via at least one LED driver system configured to selectively provide the LED current through each sequential one of the plurality of LEDs in an activated state in response to an activation signal. The at least one LED driver system includes a voltage clamp configured to maintain a substantial constant amplitude difference of a driver voltage associated with the LED current from the activated state to a deactivated state.