Abstract: This invention transforms a list of feature points in raster scan order into a list of maxima suppressed feature points. A working buffer has two more entries than the width of the original image. Each entry is assigned to an x coordinate of the original image. Each entry stores a combined y coordinate and reliability score for each feature point in the original list. This process involves a forward scan and a backward scan. For each original feature point its x coordinate defines the location within the working buffer where neighbor feature points would be stored if they exist. The working buffer initial data and the y coordinates assure a non-suppress comparison result if the potential neighbors are not actual neighbors. For actual neighbor data, the y coordinates match and the comparison result depends solely upon the relative reliability scores.

Abstract: A circuit includes a regulation control circuit. The regulation control circuit includes an error amplifier to generate a control output signal based on an error signal input and a reference input. The regulation control circuit includes a level shifter to receive a negative voltage supplied to a load and to provide a positive error signal to the error signal input of the error amplifier. A driver circuit receives the control output signal from the error amplifier and generates a drive output signal in response to the control output signal. A regulation output circuit regulates the negative voltage supplied to the load in response to the drive output signal from the driver circuit.

Abstract: A timer for creating a stable on time. The timer may have a reference voltage source, and an input voltage source. The voltage sources providing voltage that can be applied to a various circuit components such as capacitors, inductors, resistors, diodes, transistors, or other components. The reference voltage source may also be modified by a set of transistors coupled as a diode before being seen by an input of a timer comparator. The reference and input voltage source signals, which may be modified by circuit components, are compared by the timer comparator and then output as a timer control signal. The timer control signal may control a voltage converter, or the switches of a voltage converter.

Abstract: In described examples, an apparatus includes a physics cell and an electronic circuit. The physics cell includes an atomic chamber, a laser source, a modulator, a photodetector and a field coil. The electronic circuit includes a frequency synthesizer, a controller and a digital to analog converter.

Abstract: A two pin communication interface bus and control circuits are used with circuit boards, integrated circuits, or embedded cores within integrated circuits. One pin carries data bi-directionally and address and instruction information from a controller to a selected port. The other pin carries a clock signal from the controller to a target port or ports in or on the desired circuit or circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is minimal. The bus is used for communication, such as serial communication related to the functional operation of an IC or core design, or serial communication related to test, emulation, debug, and/or trace operations of an IC or core design.

Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.

Abstract: A method includes retrieving an interactive datasheet for a product and displaying, on an output device, a first view of the interactive datasheet for the product, the interactive datasheet including a first section and a second section. The method also includes adjusting, in response to receiving, by an input device of a computing device from a user, a first value of a characteristic of the product, to produce a first adjusted characteristic, and updating a model of the product, based on the first value of the characteristic of the product, to produce an updated interactive datasheet for the product. Additionally, the method includes updating the first view of the interactive datasheet for the product displayed on the output device, the first view, based on the updated interactive datasheet for the product and storing, in the memory, the updated interactive datasheet for the product, in response to receiving an indication by the user.

Abstract: For producing a low-power, low-phase noise oscillating signal using a self-injection locking oscillator, examples include: producing, using an oscillator, a signal having a base frequency component, an Mth harmonic component and a Pth harmonic component, in which M and P are selected integers and M>P>1; filtering the signal through one or more bandpass filters including at least two resonators, the filters having Q factor ?5, the filters configured to pass the Mth and Pth harmonic components; multiplying the filtered Mth and Pth harmonic components together to produce a multiplied signal, and filtering the multiplied signal using a low pass filter to pass a difference between the filtered Mth and Pth harmonic components, the difference including a filtered beat frequency waveform; and injecting the filtered beat frequency waveform into the oscillator to injection lock the signal to the filtered beat frequency waveform.

Abstract: A method for coding unit partitioning in a video encoder is provided that includes performing intra-prediction on each permitted coding unit (CU) in a CU hierarchy of a largest coding unit (LCU) to determine an intra-prediction coding cost for each permitted CU, storing the intra-prediction coding cost for each intra-predicted CU in memory, and performing inter-prediction, prediction mode selection, and CU partition selection on each permitted CU in the CU hierarchy to determine a CU partitioning for encoding the LCU, wherein the stored intra-prediction coding costs for the CUs are used.

Abstract: The present invention provides a receiver. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter having multiple antennas and capable of providing channel estimates. The receiver also includes a feedback generator portion configured to provide to the transmitter a pre-coder selection for data transmission that is based on the channel estimates, wherein the pre-coder selection corresponds to a grouping of frequency-domain resource blocks. The present invention also provides a transmitter having multiple antennas. In one embodiment, the transmitter includes a transmit portion coupled to the multiple antennas and capable of applying pre-coding to a data transmission for a receiver. The transmitter also includes a feedback decoding portion configured to decode a pre-coder selection for the data transmission that is fed back from the receiver, wherein the pre-coder selection corresponds to a grouping of frequency-domain resource blocks.

Abstract: Described examples provide a method to evaluate reliability of hail grid array products in which an interconnect stress test is performed that passes current through outer layer micro-vias of a test coupon portion of a production panel that is soldered to a printed circuit board, and the reliability of ball grid array products manufactured using package substrate portions of the production panel is evaluated according to the results of the interconnect stress test. A test coupon includes a rigid core material layer, dielectric layers laminated between copper layers above and below the core material layer, conductive micro-vias that extend through at least one of the dielectric layers between two of the copper layers, and conductive land pads on an outer one of the dielectric layers, the conductive land pads individually contacting one of the micro-vias.

Abstract: A circuit includes an isolator that provides isolated signal communications between a host-side circuit and a converter-side circuit. The isolated signal communications include a conversion start signal generated in the host-side circuit passing through the isolator to become an isolated conversion start signal in the converter-side circuit. The isolated signal communications includes an isolated system clock generated in the converter-side circuit passing through the isolator to become a system clock in the host-side circuit. A sampling clock generator in the host-side circuit generates the conversion start signal based on the system clock. A logic circuit in the converter-side circuit re-clocks the isolated conversion start signal through the logic circuit.

Abstract: Systems and methods for performing Census Transforms that includes an input from an image, with a support window created within the image, and a kernel within the support window. The Census Transform calculations and comparisons are performed within the kernel windows. A new Census Transform is disclosed which always inverts a previously made comparison. This new approach can be demonstrated to be equivalent to, applying the original Census Transform, on a pre-processed input kernel, where the pre-processing step adds a fractional position index to each pixel within the N×N kernel. The fractional positional index ensures that no two pixels are equal to one another, and thereby makes the Original Census algorithm on pre-processed kernel same as the new Census algorithm on original kernel. The hardware design for this new Census Transform kernel allows for an always invert of previous comparison system resulting in reduced hardware and power consumption.

Abstract: In one aspect of the disclosure, a semiconductor package is disclosed. The semiconductor package includes a lead frame. A semiconductor die is attached to a first side of the lead frame. A protective shell covers at least a first portion of the first surface of the semiconductor die. The protective shell comprises of ink residue. A layer of molding compound covers an outer surface of the protective shell and exposed portion of the first surface of the semiconductor die. A cavity space is within an inner space of the protective shell and the first portion of the top surface of the semiconductor die.

Abstract: A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Abstract: A system includes a controller to provide at least one control output to an automated system in response to a control command received at a control input of the controller. The control output controls the operation of the automated system based on the control command. A signature analyzer generates the control command to the controller and receives an impedance signature related to a property of a material or object encountered by the automated system. The signature analyzer compares the impedance signature to at least one comparison signature to determine the property of the material or object. The signature analyzer adjusts the control command to the controller to control the operation of the automated system based on the determined property.

Abstract: A gesture recognition system is shown using a 77 GHz FMCW radar system. The signature of a gesturing hand is measured to construct an energy distribution in velocity space over time. A gesturing hand is fundamentally a dynamical system with unobservable “state” (i.e. the type of the gesture) which determines the sequence of associated observable velocity-energy distributions, therefore a Hidden Markov Model is used to for gesture recognition. A method for reducing the length of the feature vectors by a factor of 12 is also shown, by re-parameterizing the feature vectors in terms of a sum of Gaussians without decreasing the recognition performance.

Abstract: A semiconductor system (900) has a flat interposer (510) with a first surface (401a) in a first plane, a second surface (401b) in a parallel second plane, and a uniform first height (401) between the surfaces; the interposer is patterned in metallic zones separated by gaps (412, 415), the zones include metal of the first height and metal of a second height (402) smaller than the first height; an insulating material fills the gaps and the zone differences between the first and the second heights. Semiconductor chips of a first (610) and a second (611) set have first terminals attached to metallic zones of the first interposer surface while the chips of the second set have their second terminals facing away from the interposer. A first leadframe (700) is attached to the second terminals of the second set chips, and a second leadframe (800) is attached to respective metallic zones of the second interposer surface.