Abstract: A method for fabricating an integrated circuit includes providing a partitioned chemical-mechanical planarization (CMP) model having a plurality of model parameters that include (i) device specific model parameters and (ii) at least one common parameter. (i) include a pre-CMP thickness of a film including a first material on an in-process device, a post-CMP target thickness for the film on the in-process device, and device group properties that account for device structure for the in-process device. (ii) includes a polish rate from an unpatterned pilot wafer having a second material thereon. The second material need not be the same as the first material. The polish time is automatically determined using the partitioned CMP model. A CMP process is performed on a patterned product wafer having a plurality of the in-process devices using a recipe including the polish time.

Abstract: A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.

Abstract: A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.

Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal.

Abstract: An oscillator is provided with an oscillator circuit having tank circuit terminals for coupling to a tank circuit. A microelectromechanical system (MEMS) resonator serves as a tank circuit. The MEMS resonator is coupled to the oscillator circuit using a transformer with a primary coil coupled to the oscillator tank circuit terminals and a secondary coil coupled to the MEMS resonator terminals, wherein the transformer has a turns ratio of N:1 and N is greater than 1.

Abstract: Touch/key sensing with N-1 key scan averaging, for use with an N-key touch input apparatus, including a key matrix of N touch-key sense circuits, including: (a) continuously scanning the key matrix at a first bandwidth to determine a respective touch-key baseline sense signal, independent of a key-press condition, and a related touch-key baseline value based on successive baseline sense signals; and (b) during successive key-scan periods, scanning the key matrix at a second bandwidth greater than the first bandwidth, and for each touch key N, determining a touch-key sense signal, generating an N-1 key-scan average value by averaging the touch-key baseline values for the other N-1 touch keys, comparing the Nth touch-key sense signal to a key-press threshold based on the N-1 key-scan average value; and (c) signaling a key-press condition if the touch-key sense signal is greater in magnitude than the N-1 key-scan average value by the key-press threshold.

Abstract: A semiconductor die. The die comprises a level shifter coupled to a positive differential input and to a negative differential input comprising a first operational amplifier, wherein the first operational amplifier is configured to generate an internal common mode voltage coupled to a positive differential output and to a negative differential output, a positive alternating current (AC) coupled feed-forward path comprising a first capacitor coupled to the positive differential input and to the positive differential output, a negative AC coupled feed-forward path comprising a second capacitor coupled to the negative differential input and to the negative differential output, a positive direct current (DC) feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the positive differential output, and a negative DC feed-forward path coupled to the differential input, to the internal common mode voltage sense node, and to the negative differential output.

Abstract: In described examples of a circuit that operates as a low-power ideal diode, and an IC chip that contains the ideal diode circuit, the circuit includes: a first P-channel transistor connected to receive an input voltage on a first terminal and to provide an output voltage on a second terminal; a first amplifier connected to receive the input voltage and the output voltage and to provide a first signal that dynamically biases a gate of the first P-channel transistor as a function of the voltage across the first P-channel transistor; and a second amplifier connected to receive the input voltage and the output voltage and to provide a second signal that acts to turn off the gate of the first P-channel transistor responsive to the input voltage being less than the output voltage.

Abstract: An integrated circuit includes an enable circuit and a main circuit. The enable circuit is configured to receive a supply voltage and an enable signal at a first voltage level, generate a start voltage by clamping the supply voltage to a threshold voltage level that is less than the supply voltage and generate an enable intermediate signal at a second voltage level that is less than the first voltage level and limited by the start voltage. In response to the enable intermediate signal being generated at the second voltage level, the enable circuit is configured to generate a start signal (such as a current). In response to the start signal being generated, the enable circuit is configured to generate an output signal at a third voltage level that is less than the first voltage level. The main circuit is configured to utilize the output signal as a supply voltage rail.

Abstract: A system, method, and silicon chip package for providing connections between a die of a silicon chip package and external leads of the silicon chip package is disclosed. The connections are formed using a pre-mold etched with a trace pattern. The trace pattern provides rigid traces that connect the die with the external leads.

Abstract: A microelectronic device is formed by forming a platinum-containing layer on a substrate of the microelectronic device. A cap layer is formed on the platinum-containing layer so that an interface between the cap layer and the platinum-containing layer is free of platinum oxide. The cap layer is etchable in an etch solution which also etches the platinum-containing layer. The cap layer may be formed on the platinum-containing layer before platinum oxide forms on the platinum-containing layer. Alternatively, platinum oxide on the platinum-containing layer may be removed before forming the cap layer. The platinum-containing layer may be used to form platinum silicide. The platinum-containing layer may be patterned by forming a hard mask or masking platinum oxide on a portion of the top surface of the platinum-containing layer to block the wet etchant.

Abstract: A method includes forming a plurality of layers of an oxide and a metal on a substrate. For example, the layers may include a metal layer sandwiched between silicon oxide layers. A non-conductive structure such as glass is then bonded to one of the oxide layers. An antenna can then be patterned on the non-conductive structure, and a cavity can be created in the substrate. Another metal layer is deposited on the surface of the cavity, and an iris is patterned in the metal layer to expose the one of the oxide layers. Another metal layer is formed on a second substrate and the two substrates are bonded together to thereby seal the cavity.

Abstract: An encapsulated integrated circuit is provided that includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. An electromagnetic interference (EMI) shield is provided by a photonic bandgap (PBG) structure that is included within the encapsulation material. The PBG structure is configured to have a photonic bandgap with a frequency range approximately equal to a range of frequencies that may cause EMI.

Abstract: A method of semiconductor device packaging to form a packaged semiconductor device includes providing (i) a vertical power semiconductor device die including a semiconductor substrate including a control node, a source or emitter on a top side or on a bottom side of the substrate, and a drain or a collector on another of the top side the bottom side, a backside metal (BSM) layer on the bottom side, and (ii) a leadframe. The leadframe includes a patterned die pad that includes a common continuous base portion and a two-dimensional array of spaced apart posts extending up from the base portion, with a separate solder cap on a top of the posts. The BSM layer is placed on the solder caps, and reflow processing bonds the BSM layer to the solder caps.

Abstract: Disclosed examples include differential amplifier circuits and variable neutralization circuits for providing an adjustable neutralization impedance between an amplifier input node and an amplifier output node, including neutralization impedance T circuits with first and second impedance elements in series between the amplifier input and output, and a third impedance element, including a first terminal connected to a node between the first and second impedance elements, and a second terminal connected to a transistor. The transistor operates according to a control signal to control the neutralization impedance between the amplifier input node and the amplifier output node.

Abstract: A method of channel access for a radio device in an asynchronous channel hopping wireless network. A backoff time is set from an Interference Avoidance Delay plus a random backoff time for transmissions from the radio device. For initial frame transmissions, an initial value for a number of backoffs (nb) and initial number of preamble detection backoffs (npdb) is set. After waiting for expiring of the initial backoff time and provided a current npdb_value<a predetermined maximum npdb value, a first CCA is performed on the radio device's receive (Rx) channel, and a value for npdb is incremented following a failure. A second CCA is performed on a target radio device's Rx channel, wherein a value for nb is incremented following a failure. Provided a not busy is determined in the second CCA the radio device transmits a frame on the target radio device's Rx channel.

Abstract: A level shifter with reduced propagation delay. A level shifter includes a signal input terminal, a first signal output node, a first transistor, a second transistor, a third transistor, and a first capacitor. The first transistor includes a control terminal coupled to the signal input terminal. The second transistor includes an output terminal coupled to an input terminal of the first transistor. The first capacitor includes a bottom plate coupled to an input terminal of the second transistor. The third transistor includes a control terminal coupled to a top plate of the first capacitor, and an output terminal coupled to the first signal output node.

Abstract: A circuit includes a first power transistor including a first control input and first and second current terminals. The circuit includes a second power transistor including a second control input and third and fourth current terminals. Third current terminal couples to the first current terminal, and the fourth current terminal couples to the second current terminal at an output node. An error amplifier generates an error signal based on a difference between a reference voltage and an output voltage on the output node. An adaptive buffer couples to an output of the error amplifier and couples to the first and second control inputs. The adaptive buffer causes the first power transistor to be on through a range of output current and to cause the second power transistor to be on through some, but not all, of the range of output current.

Abstract: Disclosed embodiments include a base station. The base station includes a receiver that receives a channel quality report identifying one or more particular sub-bands in a first frequency band that, when used to transmit information, causes interference in one or more channels of a second frequency band that is adjacent to the first frequency band. The base station further includes a processor that selects one or more sub-bands in the first frequency band to assign based on the channel quality report, the selected sub-band(s) avoiding the one or more particular sub-bands identified in the channel quality report. Additionally, the base station includes a transmitter that sends a sub-band assignment for the selected sub-band(s). The first frequency is a Long Term Evolution (LTE) frequency and the base station is an eNodeB base station in one embodiment.

Abstract: An electronic device, e.g. an integrated circuit, includes one or more test modules each having first and second pairs of contact pads arranged along a first axis, and a third pair of contact pads arranged along a second axis parallel to the first axis. A first connection bus connects contact pads in the first pair, a second connection bus connects contact pads in the second pair, and a third connection bus connects contact pads of the third pair. A first device under test (DUT) is connected between the first connection bus and the third connection bus, and a second DUT is connected between the second connection bus and the third connection bus.