Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: Channel state information (CSI) feedback in a wireless communication system is disclosed. User equipment transmits a CSI feedback signal via a Physical Uplink Control CHannel (PUCCH). If the UE is configured in a first feedback mode, the CSI comprises a first report jointly coding a Rank Indicator (RI) and a first precoding matrix indicator (PMI1), and a second report coding Channel Quality Indicator (CQI) and a second precoding matrix indicator (PMI2). If the UE is configured in a second feedback mode, the CSI comprises a first report coding RI, and a second report coding CQI, PMI1 and PMI2. The jointly coded RI and PMI1 employs codebook sub-sampling, and the jointly coding PMI1, PMI2 and CQI employs codebook sub-sampling.

Abstract: An oscillator architecture with pulse-edge tuning to control the pulse rising and falling edges (such as for duty cycle correction), including a signal generator with a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Pulse-edge tuning circuitry includes a high-side tuning PMOS transistor between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs to provide tuning control signals to the tuning FETs. In an example application, the oscillator design is adapted for a direct conversion RF signal chain (TX and/or RX) including an I-Path and a Q-Path: the signal generator generates ±I and ±Q differential signal frequencies.

Abstract: A semiconductor device (100) comprising a leadframe (120) having an assembly pad (121) in a first horizontal plane (180), the pad's first surface (121a) with a semiconductor chip (110) attached; further a plurality of leads (122) in a parallel second horizontal plane (190) offset from the first plane in the direction of the attached chip, the leads having a third surface (122a) with bonding wires, and an opposite fourth surface (122b); a package (140) encapsulating leadframe, chip, and wires, the package having a fifth surface (140a) parallel to the first and second planes; a plurality of recess holes (150) in the package, each hole stretching from the fifth surface to the fourth surface of respective leads; and solder (160) filling the recess holes, the solder attached to the fourth lead surface and extending to the fifth package surface.

Abstract: A voltage-to-current converter that reduces third harmonic distortion. An amplifier includes an input stage. The input stage includes a first voltage-to-current conversion stage and a second voltage-to-current conversion stage. The first voltage-to-current conversion stage is configured to provide an input to output gain with compressive nonlinearity. The second voltage-to-current stage is cascaded with the first voltage-to-current conversion stage. An input of the second voltage-to-current stage is connected to an output of the first voltage-to-current conversion stage. The second voltage-to-current conversion stage is configured to provide an input to output gain with expansive nonlinearity.

Abstract: A flow meter ultrasonically measures fluid velocity in a pipe and ultrasonically transmits fluid flow data along the pipe. An ultrasonic transducer used for fluid velocity measurement may optionally also be used for communication of flow data, and optionally, the ultrasonic frequency for fluid velocity measurement may be the same as the ultrasonic frequency for communication of flow data.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to regulate a switched mode power supply. An example power converter includes a first comparator, a ramp generator coupled to a first input of the first comparator, and a current balance circuit coupled to the ramp generator, the current balance circuit including a transistor including a first current terminal, a second current terminal, and a gate, a multiplier circuit coupled to the first current terminal, a second comparator coupled to the gate, a first current source coupled to the first current terminal and the multiplier circuit, and a second current source coupled to the second current terminal and the second comparator.

Abstract: A method for communicating in a wireless sensor network (WSN) is described. Using control logic, a first wireless transceiver is caused to transmit a wireless packet to a node in a wireless sensor network. The control logic bases its causing on a transmission coinciding with a break in transmission for a second wireless network, such that the transmission from the first wireless transceiver does not coincide with transmissions made on the second wireless network. Time synchronized channel hopping (TSCH) slot frames for wireless packet transmission in the wireless sensor network are caused to be time offset if the first wireless transceiver is utilizing TSCH. Wake up sequence transmissions for the wireless sensor network are caused to be time offset if the first wireless transceiver is utilizing coordinated sampled listening (CSL).

Abstract: A long-range power-efficient multiple-band identification system and method includes, for example, a base-station control module and paired electronic key fob. The base-station control module and paired electronic key fob is arranged to provide a UHF (ultra-high frequency) wake transmitter for transmitting a wakeup signal in a UHF frequency range to the paired electronic key. When in range, the electronic key is awakened by the wakeup signal and in response transmits an acknowledgment reply to the base-station control module. After receiving the acknowledgment, the base-station control module transmits a relatively high power localization signal for determining an electronic key location.

Abstract: A transistor device includes a field plate extending from a source contact layer and defining an opening above a gate metal layer. Coplanar with the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. Meanwhile, the opening allows a gate runner layer above the field plate to access and connect to the gate metal layer, which helps reduce the resistance of the gate structure. By vertically overlapping the metal gate layer, the field plate, and the gate runner layer, the transistor device may achieve fast switching performance without incurring any size penalty.

Abstract: A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L?1 remaining possible distinct data values, wherein each of the L?1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L?1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L?1 remaining possible distinct data values in the N samples, and encoding the L?1 coding vectors.

Abstract: A processor is provided for use with a memory having selectable memory areas. In an example, the processor includes a memory area selection circuit (MMU) to select one of the selectable memory areas, and an instruction fetch circuit to fetch a target instruction at an address from the selected memory area. The processor includes an execution circuit (Pipeline) to execute instructions from the instruction fetch circuit and to execute a first instruction for changing the selection by the MMU to a second selectable memory area. The Pipeline executes a branch instruction that points to a target instruction, where access to the target instruction depends on actual change of selection to the second memory area. The processor also includes a logic circuit to ensure fetch of the target instruction in response to the branch instruction after actual change of selection. Other circuits, devices, systems, apparatus, and processes are also disclosed.

Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

Abstract: Complementary high-voltage bipolar transistors in silicon-on-insulator (SOI) integrated circuits is disclosed. In one disclosed embodiment, a collector region is formed in an epitaxial silicon layer disposed over a buried insulator layer. A base region and an emitter are disposed over the collector region. An n-type region is formed under the buried insulator layer (BOX) by implanting donor impurity through the active region of substrate and BOX into a p-substrate. Later in the process flow this n-type region is connected from the top by doped poly-silicon plug and is biased at Vcc. In this case it will deplete lateral portion of PNP collector region and hence, will increase its BV.

Abstract: A method for making integrated circuit (IC) packages includes providing a leadframe strip having a plurality of leadframe units and providing the leadframe strip to an operating station. The operating station is operable to perform one or more tests on the plurality of leadframe units in the making of IC packages. The method includes obtaining a database that has the locations of leadframe units in the leadframe strip stored in the database. The method also includes performing the one or more tests on the plurality of leadframe units and updating the database in response to the results of the testing.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: An integrated circuit device is disclosed that includes an sense amplifier having first and second input terminals, a compensation network including a first compensation circuit coupled to the first input terminal of the sense amplifier and a second compensation circuit coupled to the second input terminal of the sense amplifier, and a latch circuit operable to selectively enable either one of the first and second compensation circuits, but not both of the first and second compensation circuits simultaneously.

Abstract: A circuit comprising a NMOS having a gate coupled to a first node and a source terminal coupled to a second node, a second NMOS having a gate coupled to the second node and a source terminal coupled to an output node, a PMOS having a gate coupled to a third node, a drain terminal coupled to a fourth node, and a source terminal coupled to a fifth node, and a second PMOS having a gate coupled to the fourth node, a drain terminal coupled to the output node, and a source terminal coupled to the fifth node. The circuit also includes a voltage protection sub-circuit coupled to the first node, a fast turn-off sub-circuit coupled to the output node, a fast turn-on sub-circuit coupled to the third and fourth nodes, and a node initialization sub-circuit coupled to the first, second, and fourth nodes and the fast turn-on sub-circuit.

Abstract: Instructions for 32-bit arithmetic support using 16-bit multiply and 32-bit addition without a barrel shifter. Illustrative instructions include operations that include receiving a first 32-bit operand, receiving a second 32-bit operand, shifting the second 32-bit operand right 16 or 15 bits to obtain a shifted second 32-bit operand, and adding the shifted second 32-bit operand and the first 32-bit operand to generate a 32-bit sum.

Abstract: A wireless transmission system included at least one user equipment and a base station. The base station is operable to form a downlink control information block, modulate the downlink control information, precode the modulated downlink control information, and transmit the precoded, modulated downlink control information on at least one demodulation reference signal antenna port to the at least one user equipment. The precoded, modulated downlink control information is mapped to a set of N1 physical resource block pairs in a subframe from an orthogonal frequency division multiplexing symbol T1 to and orthogonal frequency division multiplexing symbol T2.