Abstract: A power provider circuit includes a plurality of power delivery controllers, a single stage power supply, and control circuitry. Each of the plurality of power delivery controllers is configured to provide power to a detachable device. The single stage power supply is configured to generate the power for provision to the detachable devices, and to provide the power at a plurality of selectable voltages. The control circuitry configured to select a given voltage of the plurality of selectable voltages to be made available via all of the power delivery controllers based on power utilization capabilities and other optional status indications reported by the detachable devices.

Abstract: A touch-scroll apparatus can provide touch-scroll input/functionality, such as for a mobile communication device (as an example application). The touch-scroll apparatus includes a multi-coil sensor assembly including multiple sense inductor coils (for example, three). A sensor slot is formed in a portion of the device case (such as a device side-wall), defining a touch-scrolling surface/area at the exterior of the device. The sidewall slot is dimensioned to receive and position the touch-scrolling multi-coil sensor assembly relative to the touch-scrolling surface/area. Inductive sensor electronics is coupled to the multiple touch-scroll sense inductor coils to detect scrolling movement and direction based on signal output from the sensor inductor coil signals (such as changes in coil inductance), including for each a peak signal corresponding to maximum deflection of the touch-scrolling surface/area opposite the sense inductor coil.

Abstract: An interface device includes an NPN structure along a horizontal surface of a p-doped substrate. The NPN structure has a first n-doped region coupled to an output terminal, a p-doped region surrounding the first n-doped region and coupled to the output terminal, and a second n-doped region separated from the first n-doped region by the p-doped region. The interface device also includes a PNP structure along a vertical depth of the p-doped substrate. The PNP structure includes the p-doped region, an n-doped layer under the p-doped region, and the p-doped substrate. Advantageously, the interface device can withstand high voltage swing (both positive and negative), prevent sinking and sourcing large load current, and avoid entering into a low resistance mode during power down operations.

Abstract: A method, system and apparatus is disclosed for auto-tuning a circuit associated with an upstream transducer (UPT) and a circuit associated with a downstream transducer (DNT) for reciprocal operation in an ultrasonic flowmeter. The method includes exchanging signals between the upstream transducer and the downstream transducer; comparing at least one of respective maximum amplitudes of an upstream signal and a downstream signal and respective center frequencies of a Fast Fourier Transform (FFT) of the upstream signal and the downstream signal; and responsive to determining that at least one of the respective maximum amplitudes and the respective center frequencies do not match, correcting the mismatch.

Abstract: An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance, ESD protection diode in parallel with a shallow trench isolated, low capacitance, ESD protection diode.

Abstract: A time-to-digital converter circuit includes a logic gate coupled to receive a first trigger signal indicative of a first clock signal and a second trigger signal indicative of a second clock signal. The logic gate is to generate a logic gate output signal responsive to the earlier of the first or second trigger signals to be a logic high. A synchronization circuit is included and is coupled to the logic gate and is configured to synchronize the logic gate output signal to a third clock to produce a synchronization output signal. A counter circuit counts pulses of the synchronization output signal.

Abstract: Methods and apparatus for isolation barrier with magnetics. In an example arrangement, an apparatus includes an isolation laminate including a dielectric core having a first surface and a second surface opposed to the first surface; at least one conductive layer configured as a first transformer coil overlying the first surface; a first dielectric layer surrounding the at least one conductive layer; a first magnetic layer overlying the at least one conductive layer; at least one additional conductive layer configured as a second transformer coil overlying the second surface; a second dielectric layer surrounding the at least one additional conductive layer; and a second magnetic layer overlying the at least one additional conductive layer. Methods for forming the isolation barriers and additional apparatus arrangements are also disclosed.

Abstract: A method of determining the angular position (?) of a rotor of an N-phase permanent magnet motor (PMM) includes providing a processor having an associated memory, wherein the memory stores an angular position determination (APD) equation or hardware is included implementing the APD equation. The APD equation determines the angular position from N-phase measurements obtained from the stator windings associated with each of the N-phases. A voltage or a current is forced upon the stator terminals of the stator windings for each of the N-phases, a resulting stator current or stator voltage is sensed to provide the N-phase measurements responsive to the forcing of the voltage or current, and the APD equation is used to determine the angular position from the N-phase measurements.

Abstract: An integrated circuit which includes a field-plated FET is formed by forming a first opening in a layer of oxide mask, exposing an area for a drift region. Dopants are implanted into the substrate under the first opening. Subsequently, dielectric sidewalls are formed along a lateral boundary of the first opening. A field relief oxide is formed by thermal oxidation in the area of the first opening exposed by the dielectric sidewalls. The implanted dopants are diffused into the substrate to form the drift region, extending laterally past the layer of field relief oxide. The dielectric sidewalls and layer of oxide mask are removed after the layer of field relief oxide is formed. A gate is formed over a body of the field-plated FET and over the adjacent drift region. A field plate is formed immediately over the field relief oxide adjacent to the gate.

Abstract: A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Abstract: An apparatus includes a substrate containing a cavity and a dielectric structure covering at least a portion of the cavity. The cavity is hermetically sealed. The apparatus also may include a launch structure formed on the dielectric structure and outside the hermetically sealed cavity. The launch structure is configured to cause radio frequency (RF) energy flowing in a first direction to enter the hermetically sealed cavity through the dielectric structure in a direction orthogonal to the first direction. Various types of launch structures are disclosed herein.

Abstract: An electronic circuit system with an input for receiving an analog signal having a frequency and comprising noise, that noise including input referred noise, and the noise fluctuates in a range. The system also comprises a signal path with: (i) an analog to digital converter for providing a digital output value in response to a clock period; (ii) a feedback node; and (iii) circuitry for limiting a signal swing at the feedback node, during a period of the clock period, to be no greater than an RMS value of the noise. The analog to digital converter is further for providing the digital output value in response to the analog signal and the signal swing at the feedback node.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

Abstract: An apparatus to secure a sensor assembly for a device touch button (such as for a mobile communications device). A touch sensor slot forms a part of the device case interior at a back-side of the touch button surface, and is configured to position the touch sensor (such as a sense coil inductor) relative to the associated touch button. A touch sensor spring clip is inserted within the touch sensor slot to flexibly urge the touch sensor toward the front-side surface of the touch sensor slot (back-side of the touch button surface). The touch sensor can include front-side spacers to maintain a sensing gap between the touch sensor and the touch button surface, and can include a sensor stiffener at the back-side surface of the touch sensor assembly, the touch sensor spring clip contacting the sensor stiffener. The touch sensor assembly can comprise a flex circuit PCB assembly.

Abstract: A driver circuit includes two high-side switches and a single low-side switch, output inductor, and output capacitor. By having multiple high-side switches, the driver can regulate power from multiple charging devices. The high-side switches share a channel with an input capacitor for that channel and the channels are connected to the low-side switch at a common node. When the capacitor for one of the channels becomes charged quickly, the capacitor of the other channel will balance itself with the charged capacitor. To avoid damaging the high-side switches, a low-impedance bridge and driver circuit is connected between the channels.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Abstract: This invention is an improvement of a Hierarchical Do-Dag based RPL (H-DOC) network configuration where the network address of each node corresponds to its location within the hierarchical network. Network addresses are initialized hierarchically. Candidate patent nodes signal availability. Candidate child nodes respond to a selected candidate parent node with a temporary address. The selected candidate parent node acknowledges selection and communicates a hierarchical address for the child node in a transmission to the temporary address. The child node changes its address to the hierarchical address from the parent node. When a node switches parent nodes, it signals the old parent node to deallocate it as a child node, and then signals a selected candidate parent node with a temporary address.

Abstract: A circuit includes an oscillator having a driver and a resonator. The driver receives a supply voltage at a supply input and provides a drive output to drive the resonator to generate an oscillator output signal. A power converter receives an input voltage and generates the supply voltage to the supply input of the driver. A temperature tracking device in the power converter controls the voltage level of the supply voltage to the supply input of the driver based on temperature such that the supply voltage varies inversely to the temperature of the circuit.

Abstract: A method for enabling physical controls in a digital system is provided that includes receiving an image of an illuminated surface in the digital system, wherein the image is captured by a camera in the digital system, determining a state of a physical control mounted on the illuminated surface by analyzing the image; and outputting an indication of the state of the physical control.