Abstract: Apparatus and methods are disclosed for examining how reliability in an RF power amplifier circuit changes as a function of variation of the input to output voltage swings. Two output transistors that varying greatly in the size of their respective channel widths are provided for independently evaluating impacts on the output waveform. The gate control for the smaller transistor is separate from the gate control to the larger transistor. The gate and drain stress can thus be adjusted and evaluated independently.

Abstract: A rectifier circuit for use in an energy harvesting application in which mechanical energy is converted into electrical energy by using an AC generator using an active rectifier bridge with a pair of input terminals adapted to be connected to an output of the AC generator and a pair of output terminals, an inductor connected across the output terminals of the active rectifier bridge and a storage capacitor. A pair of output switches selectively connects the storage capacitor across the inductor. A controller controls the active rectifier bridge and the pair of output switches such that in successive switching cycles within any half wave of AC input voltage from the output of the AC generator the inductor is first loaded by current from the output of the AC generator and then discharged into the storage capacitor.

Abstract: According to one embodiment, a micro-optical device includes an electro-optical circuit and an annular frame disposed on a surface of a substrate. The electro-optical circuit has an active region that is encapsulated by a window and an interconnect region adjacent at least one edge of the electro-optical circuit. The annular frame extends around an outer periphery of the window and is separated from the window by a gap, the annular frame and the electro-optical circuit form a cavity for placement of a plurality of bonding wires the interconnect that electro-optical circuit to the substrate.

Abstract: An improved method for optimizing layer registration during lithography in the fabrication of a semiconductor device is disclosed. In one example, the method comprises optimizing contact layer registration of an SRAM device having a plurality of transistors having active and gate region features extending generally along a channel length (X) direction and a channel width (Y) direction, respectively. The method comprises aligning a contact layer to a gate layer in the channel length direction (X), using gate layer overlay marks to control the alignment of the contact layer in the channel length direction (X) of the semiconductor device. The method further includes aligning the contact layer to an active layer in the channel width direction (Y), using active layer overlay marks to control the alignment of the contact layer in the channel width direction (Y) of the semiconductor device.

Abstract: Disclosed is an electrostatic discharge (ESD) protection validator, a method of validating ESD protection for an IC and an ESD validation system. In one embodiment, the ESD protection validator includes: (1) a circuit analyzer configured to compare component information of the IC with predefined ESD protection elements to identify ESD cells of the IC and (2) an ESD cell verifier configured to compare physical attributes associated with the identified ESD cells to ESD protection requirements and determine compliance therewith.

Abstract: An electronic device includes a DC-DC converter for voltage conversion in a slave mode an in a master mode and including a phase locked loop. The phase locked loop comprises a controlled oscillator, a filter having an integration capacitor coupled to a control input of the controlled oscillator, a charge pump, and a phase frequency detector. In the slave mode, the controlled oscillator, the filter, the charge pump and the phase frequency detector are coupled to operate as the phase locked loop. There is a comparator coupled with an input to a control input of the controlled oscillator and with an output to the charge pump. In the master mode, the comparator is configured to control the charge pump in response to a control signal at the control input of the controlled oscillator when the phase frequency detector is switched off so as to perform a modulation of the control signal at the control input of the controlled oscillator by charging and discharging the integration capacitor.

Abstract: A method of patterning a plurality of polysilicon structures includes forming a polysilicon layer over a semiconductor body, and patterning the polysilicon layer to form a first polysilicon structure using a first patterning process that reduces line-edge roughness (LER). The method further includes patterning the polysilicon layer to form a second polysilicon structure using a second patterning process that is different from the first patterning process after performing the first patterning process.

Abstract: A method of forming a resist feature includes forming a resist layer over a semiconductor body, and selectively exposing the resist layer. The method further includes performing a first bake of the selectively exposed resist layer, and developing the selectively exposed resist layer to form a resist feature having a corner edge associated therewith, thereby exposing a portion of the semiconductor body. A second bake of the developed selectively exposed resist layer is then performed, thereby rounding the corner edge of the resist feature.

Abstract: The present invention relates to a method of performing a variable film etch using a variable thickness photomask material. Essentially, a thickness of an adjustable film layer is measured and converted into a contour map of film thickness over a region of a semiconductor body (e.g., wafer). An etch mask layer (e.g., photoresist) is then formed above the adjustable film layer and is selectively patterned by a reticleless exposure system (e.g., DMD exposure system). The selective patterning subjects different regions of the etch mask layer to varying exposure times dependent upon the thickness of the underlying adjustable film. The more etching needed to provide the underlying film to a nominal thickness, the longer the exposure of the etch mask. Therefore, the resultant etch mask, after exposure, comprises a topology allowing for various degrees of selective etching of the underlying film resulting in a uniform film.

Abstract: One embodiment relates to a computer method of providing an electronic mask set for an integrated circuit (IC) layer. In the method, a first electronic mask is generated for the IC layer. The first electronic mask includes a first series of longitudinal segments from the IC layer, where the first series has fewer than all of the longitudinal segments in the IC layer. A second electronic mask is also generated for the IC layer. The second electronic mask includes a second series of longitudinal segments from the IC layer, where the second series has fewer than all of the longitudinal segments in the IC layer and differs from the first series. The first and second masks are generated so a coupling segment extends traverse to the first direction and couples one longitudinal segment on the IC layer to another longitudinal segment on the IC layer.

Abstract: A digital signal processor (DSP) includes an instruction buffer queue (IBQ) with multiple lines, as well as a modifiable fetch advance parameter to specify a fetch advance setting for the IBQ. The DSP also has a control flow module. In response to execution of a program in the DSP, the control flow module may automatically determine whether a branch has been predicted for the program, or for a portion of the program. The control flow module may automatically reduce the fetch advance parameter in response to determining that a branch has been predicted for the program. Also, the control flow module may automatically increase the fetch advance setting in response to determining that no branch has been predicted for a portion of the program. Other embodiments are described and claimed.

Abstract: Apparatus and methods are disclosed for evaluating degradation of a transistor in a cross coupled pair of an RF oscillator independently. A MOS device can be coupled between a separated center-tap inductor. By appropriately sizing the MOS device and turning the MOS device on during operation of RF oscillator, a good contact can again be made that allows the oscillator to operate at design performance. By turning the MOS device off, the supplies can be separates such that I-V characteristics of both transistors of the cross-coupled pair may be obtained.

Abstract: A delay locked loop (DLL) is provided. Within this DLL is a watchdog circuit that determines whether harmonic lock is present. Based on this measurement, the watchdog circuit can provide adjustments to the DLL so as to change the length of the delay of the delay line to bring it within a predetermined range.

Abstract: According to one embodiment of the present invention a method for directing light onto a digital micromirror device is disclosed that includes the steps of directing light toward a DMD through a lens that includes a plurality of lens elements such that, absent correction, the directed light is distorted at the DMD; and compensating for the distortion of the directed light at the DMD by predistorting the directed light prior to reaching the DMD by the plurality of lens elements.

Abstract: In an embodiment, the invention provides a method for programming flash memory while maintaining a constant error correction term. A data field and forcing bits are arranged in a packing order. Next, all the forcing bits are set to a logical zero value. A first error correction term is generated using the data field and forcing bits as an input to an ECC encoding algorithm. An exclusive OR function is performed on the constant error correction term and the first error correction term creating a difference term. A forcing function is applied to the difference term creating a new value for the forcing bits. The data field and the forcing bits are written to the flash memory.

Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor replacement gates are provided for CMOS transistors. The process provides dual or differentiated work function capability (e.g., for PMOS and NMOS transistors) in CMOS processes.

Abstract: A modeler for components of an IC under ESD conditions, a method of simulating ESD behavior of an IC and an ESD simulation system. In one embodiment, the modeler includes: (1) a circuit analyzer configured to provide identified ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) a model generator configured to create linearized models of the identified ESD cells and the identified circuitry based on physical attributes associated with the identified ESD cells and the identified circuitry, wherein a combination of the linearized models represent operation of the IC component under ESD conditions.

Abstract: A dual platform communication controller, a method of controlling communication of data packets based on different communication standards and a wireless transceiver. In one embodiment, the dual platform communication controller includes: (1) a signal interpreter configured to recognize first data packets based on a first communication standard and second data packets based on a second communication standard and (2) a traffic manager coupled to the signal interpreter and configured to dynamically control communication of the second data packets including active second data packets and allocate bandwidth for communication of the first and second data packets.

Abstract: One embodiment relates to a computer method for aligning wafers processed in a semiconductor fabrication facility. In the method, a first arrangement of dies having a common functionality level is identified on a first wafer. A first alignment signature is assigned to the first wafer based on the first arrangement. A second arrangement of dies having the common functionality level is identified on a second wafer. A second alignment signature is assigned to the second wafer based on the second arrangement. The first alignment signature is compared to the second alignment signature, and the first and second wafers are selectively aligned based on a result of the comparison. Other systems and methods are also disclosed.

Abstract: The present invention relates to a method for trimming passive devices during fabrication to account for process variations. More particularly, the present invention relates to a method by which an adjustable device layer comprised within a passive device (e.g., resistor body, capacitor electrodes) can be measured and subsequently trimmed (e.g., etched to reduce size) during processing to correct for process variations. Essentially, an operational parameter is measured for a plurality of passive devices. The measurements are used to form an adjustment map for a region of a semiconductor body (e.g., wafer) comprising information pertaining to operational parameters as a function of spatial coordinates. The adjustment map is utilized by a DMD projector configured to pattern openings into a hardmask configured over the adjustable device layer. The adjustable device layer is then etched in regions not protected by the hardmask, thereby effectively trimming the passive device according to the adjustment map.