Patents Assigned to Texas Instruments
  • Publication number: 20100169845
    Abstract: An ESD protection optimizer, a method of optimizing ESD protection for an IC and an ESD protection optimization system is disclosed. In one embodiment, the ESD protection optimizer includes: (1) a circuit analyzer configured to identify ESD cells and circuitry of the IC by comparing component information of the IC with predefined ESD protection elements and predefined circuit topologies and (2) an ESD resistance determiner configured to calculate a resistance value to couple in series with the circuitry, the resistance value based on protection cell physical attributes associated with the identified ESD cells and circuitry physical attributes associated with the identified circuitry.
    Type: Application
    Filed: May 1, 2009
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Gianluca Boselli, Jonathan S. Brodsky, John E. Kunz, JR.
  • Publication number: 20100169037
    Abstract: In an embodiment, the invention provides a method for characterizing a threshold voltage of a flash memory cell. The method comprises generating a pulse train signal on flash memory IC, applying the pulse train signal to an external low-pass filter, and applying an output of the low-pass filter to the input of an external gain stage. An analog signal from the output of the gain stage is directed to a control gate of the flash memory cell. An electrical parameter of the flash memory cell is measured by an external tester.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventors: Harland Glenn Hopkins, David J. Livingston
  • Publication number: 20100169517
    Abstract: A detection circuit indicates when a source device is coupled to a sink. An interface circuit separately interfaces with the plurality of source devices and permits display identification data associated with an interfaced source device to be sent from the memory unit to the interfaced source device. A monitoring unit monitors communications between the plurality of source devices and a memory unit and generates a signal for the plurality of source devices upon identifying that the memory unit is available for storing display identification data that is associated with a remaining source device of the plurality of source devices. The signal is communicated to the control unit to cause the control unit to update the memory unit with the display identification data that is associated with the remaining source device(s). A power detection circuit powers the sink via power from a source device(s) in a low-power mode.
    Type: Application
    Filed: December 30, 2008
    Publication date: July 1, 2010
    Applicant: Texas Instruments Incorporated
    Inventor: Ajinder Pal Singh
  • Patent number: 7745067
    Abstract: Provide is a method of making a mask layout, an integrated circuit device made by a method, a computer readable medium, and a mask for forming contact holes. The method can comprise patterning a first feature along a first axis, determining a first set of areas adjacent to the first feature, wherein each of the areas in the first set of areas is within a first angle away from the first axis, and wherein each of the areas in the first set of areas is within a first distance away from the first feature, and patterning a second feature in at least one of the first set of areas so as to form a mask layout, wherein each of the first feature and the second feature are one of a virtual feature and a real feature.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: James Walter Blatchford, Scott William Jessen
  • Patent number: 7746962
    Abstract: The present invention provides a packet detector for use with a packet-based wireless receiver employing a receive antenna for P concurrently transmitted streams, where P is at least two. In one embodiment, the packet detector includes a correlation unit coupled to the single receive antenna and configured to provide a correlation function based on P acquisition fields corresponding to the P concurrently transmitted streams. Additionally, the packet detector also includes a pseudo-magnitude calculator coupled to the correlation unit and configured to calculate a packet detection metric based on the correlation function.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Michael T. DiRenzo, David P. Magee, Manish Goel
  • Patent number: 7745238
    Abstract: A method of measuring temperature across wafers during semiconductor processing includes the step of providing a correlation between a peak wafer temperature during a processing step and a change in wafer surface charge or surface potential following the processing step. A first wafer to be characterized for its peak temperature spatial distribution during the processing step is processed through the processing step. The wafer surface charge or surface potential at a plurality of locations on the first wafer are measured following the processing step. A peak temperature spatial distribution for the first wafer is then determined based on the correlation and the wafer surface charge or surface potential measured in the measuring step.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Deepak A. Ramappa, Rosa A. Orozco-Teran, Laura Matz
  • Patent number: 7746177
    Abstract: Self-biased bipolar ring-oscillator phase-locked loops with a wide tuning range are disclosed. In a particular example, an apparatus to provide a phase-locked loop is described, comprising a voltage-controlled oscillator (VCO) to provide an output clock signal having a frequency, a quantizer, a phase-frequency detector to generate an adjustment signal, and a charge pump to modify the control voltage. The example VCO includes several ring-oscillator stages, where each ring-oscillator stage includes several gain stages to provide several output currents based on a comparison of a control voltage and several corresponding threshold voltages. The example quantizer includes several comparators to generate digital signals based on the output currents. The example charge pump modifies the control voltage based on the digital signals and the adjustment signal, and includes several switching elements to increase or decrease current to the charge pump based on the digital signals.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiheng Cao, Robert Floyd Payne
  • Patent number: 7745857
    Abstract: The object of the invention is to provide a semiconductor device that can form photodiodes that do not short circuit, without damage that causes leakage, despite formation of the opening part, and its manufacturing method. The second semiconductor layer (12, 16) of the second conductivity type is formed on the main surface of the first semiconductor layer (10, 11) of the first conductivity type. Element-separating regions (13, 14, 15, 17) formed at least on the second semiconductor layer separate the device into the regions of plural photodiodes (PD1-PD4). Conductive layer 18 is formed on the second semiconductor layer 16 in a pattern that is divided for each of the photodiodes and is connected to the second semiconductor layer 16 along the outer periphery with respect to all of the plural photodiodes. Insulation layer (19, 21) is formed on the entire surface to cover conductive layer 18.
    Type: Grant
    Filed: March 29, 2006
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Yohichi Okumura, Hiroyuki Tomomatsu
  • Patent number: 7746612
    Abstract: One embodiment of the invention includes a power regulation system. The system comprises a power regulator configured to periodically generate a switch signal that regulates a current flow through an inductor to set a magnitude of an output voltage. The system further comprises an overvoltage protection circuit configured to monitor a peak voltage magnitude of the switch signal and to generate an overvoltage indication signal in response to the peak voltage magnitude of the switch signal exceeding a predetermined limit.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Jingwei Xu, Jian Wang, Jianbo Guo
  • Patent number: 7746894
    Abstract: In at least some embodiments, a system may comprise one or more devices configurable to communicate according to a first protocol that permits interpretation of transmitted symbols associated with a first time duration. The system may further comprise one or more devices configurable to communicate according to a second protocol that permits interpretation of transmitted symbols associated with multiple time durations. The one or more devices configurable to communicate according to the second protocol are operable to communicate using transmitted symbols associated with the first time duration and to communicate using transmitted symbols associated with a time duration that is not supported by the one or more devices configured to communicate according to the first protocol.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Markos G. Troulis, Arndt Joseph Mueller, Karl E. Fitzke
  • Patent number: 7746608
    Abstract: An ESD protection circuit (710) is guarded by a parallel first precharge elimination circuit (720) relative to an I/O pad (721) and a parallel second precharge elimination circuit (730) relative to a VDD pad (731). The precharge elimination circuits are synchronized with the ESD protection circuit to eliminate any precharge voltage to ground before an ESD pulse affects the I/O pad or VDD pad. A diode (722) is connected between I/O pad and VDD. Circuit (720) is between I/O pad and ground (740) and is powered by the same VDD. Circuit (720) includes a first resistor (723), a first nMOS transistor (724), and a first RC timer including a second resistor (725) and a first capacitor (726). Circuit (730) includes a third resistor (733), a second nMOS transistor (734), and a second RC timer including a fourth resistor (735) and a second capacitor (736).
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Chih-Ming Hung, Charvaka Duvvury
  • Patent number: 7747918
    Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7746045
    Abstract: A multi-phase power system including a plurality of Pulse Width Modulation (PWM) controllers is provided, including a first PWM controller and at least one second PWM controller. The first PWM controller is configured to generate at least one first output signal based on a first clock signal, and to insert at least one synchronizing pulse into the first clock signal, the synchronizing pulse having a predetermined characteristic differing from pulses of the first clock signal, and to provide the first clock signal including the synchronizing pulse to the second PWM controller. The second PWM controller is configured to generate at least one second output signal based on the first clock signal, and to synchronize the generation of the first and second output signals using the synchronizing pulse within the first clock signal, thereby maintaining a predetermined phase relationship between the first and second output signals.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: William Todd Harrison, Xuening Li
  • Patent number: 7747919
    Abstract: A Scan-BIST architecture is adapted into a low power Scan-BIST architecture. A generator 102, compactor 106, and controller 110 remain the same as in the known art. The changes between the known art Scan-BIST architecture and the low power Scan-BIST architecture involve modification of the known scan path into scan path 502, to insert scan paths A 506, B 508 and C 510, and the insertion of an adaptor circuit 504 in the control path 114 between controller 110 and scan path 502.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7746123
    Abstract: Various apparatuses, methods and systems for switched mode electronic circuits with reduced EMI are disclosed herein. For example, some embodiments of the present invention provide apparatuses including a power supply, an output, and a composite switch connected between the power supply and the output. The composite switch includes a plurality of transistors connected in parallel, a switch closing delay line having a plurality of switch closing outputs each connected to a control input of one of the plurality of transistors, and a switch opening delay line having a plurality of switch opening outputs each connected to one of the plurality of switch closing outputs. The switch closing delay line and switch opening delay line are connected in an order that opens the plurality of transistors in a staggered order in time and closes the plurality of transistors in a reverse staggered order in time.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Richard Knight Hester, Patrick Peter Siniscalchi
  • Patent number: 7746879
    Abstract: A deterministic access system and method is provided that may be used for gaining access to a shared communication medium in a mesh or decentralized network. The deterministic access method enables QoS prioritization for periodic data flows such as those used in streaming media or VOIP communications without the direction of a central controller. The method provides a way for network nodes to schedule communications that take into account the hidden node problem, provide priority access to the communication medium for high QoS data flows, and provide shared access to the medium for lower priority data packets during unscheduled times. The method also enables both backward and forward compatibility with network communication methods as well as interoperability between mesh networks and conventional networks.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Shantanu Kangude, Harshal Chhaya
  • Patent number: 7746182
    Abstract: Various systems, methods and apparatus for calibrating a clock generating circuit are discussed herein. As one example, a method for calibrating a voltage controlled oscillator is disclosed. The method includes fixing the control voltage of a fine tune capacitor in the voltage controlled oscillator at a predetermined level. A binary search is performed in a digital circuit for a value of a calibration word that is used to enable switched capacitors in a coarse tune capacitor bank in the voltage controlled oscillator. The calibration word is fixed at the value determined by the binary search, and the control voltage of the fine tune capacitor is released to enable adjustment of the control voltage by a feedback signal to the voltage controlled oscillator.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Sridhar Ramaswamy, Mustafa Ulvi Erdogan
  • Patent number: 7746591
    Abstract: Methods and apparatus to provide dynamically biased write drivers for hard disk drive applications are described. According to one example, a hard disk drive write system includes a drive signal generator to receive data to be written to a hard disk drive platter and to generate drive signals including a boost signal. A drive circuit is configured to receive the drive signals and to generate currents for output to the transmission line based thereon, wherein the currents include a boost current. A variable bias circuit is configured to detect the boost signal generated by the drive signal generator and to vary a bias signal provided to the impedance matching circuit based on the detection of the boost signal. In such an example arrangement, the impedance matching circuit matches impedances between the drive circuit and the transmission line in response to the bias signal provided by the variable bias circuit.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Priscilla Enid Escobar-Bowser
  • Patent number: 7746155
    Abstract: In accordance with the present invention, there is provided a circuit and method for providing a switchable strong pulldown for a power FET in an off state to avoid inadvertent or false turn ons. A strong pulldown is provided to the gate of a power FET to avoid inadvertent turn on during output swings. In other cases, the gate of the power FET is pulled down weakly to reduce EMI and voltage noise in the circuit. In a particular exemplary embodiment, the present invention provides a circuit and method for obtaining a strong pulldown on the gate of a power FET in an off state, while providing a weak pulldown during turn on to turn off transitions. The invention avoids false turn ons during fast output transitions while maintaining relatively high EMI protection.
    Type: Grant
    Filed: March 30, 2005
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventor: Eric Labbe
  • Patent number: 7746812
    Abstract: A wireless receiver operating in a wireless communication environment in which a beginning of a packet contains a repetitive sequence. The wireless receiver may compute a variance (example of a measure of variations in the cross correlation values) of cross-correlation values obtained by cross correlating a received signal and a copy of the preamble sequence starting at different time instances. When a valid packet is received, the variance of the values resulting from the cross correlation is high, otherwise the variance is low. As a result packet detection is made robust, and false packet detection due to interference signals is reduced. In an embodiment, the wireless receiver is implemented in the context of WLAN 802.11 a/g network.
    Type: Grant
    Filed: July 16, 2007
    Date of Patent: June 29, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Bijoy Bhukania, Naga Satya Srikanth Puvvada