Abstract: The present invention provides a video server. In one embodiment, the video server includes a perceptual analyzer configured to analyze frames of a video sequence and provide a video analysis file. The video server also includes a transmitter coupled to the perceptual analyzer and configured to transmit both the video sequence and the video analysis file. The present invention also provides a mobile client. In one embodiment, the mobile client includes a liquid crystal display (LCD) having a backlight and configured to provide a video sequence for the mobile client. The mobile client also includes a display processor, coupled to the LCD, configured to employ a received video analysis file to enhance at least one of a brightness and contrast of the video sequence and correspondingly reduce a backlight intensity of the backlight.

Abstract: A system for interrupt handling in Java is provided that includes an execution flow class, an execution flow scheduler, a Java virtual machine (JVM), and an interrupt handler class that extends the execution flow class. The execution flow class defines an execution flow execution method and a constructor that creates an execution flow context. The interrupt handler class defines a handler method for an interrupt and an execution flow execution method that overrides the execution flow execution method of the execution flow class. An interrupt handler object is instantiated using the interrupt handler class, the constructor creates an execution flow context for the handler method, and when the interrupt is signaled, the JVM invokes a native execution flow activation method in the execution flow scheduler to switch to the handler execution flow context and the execution flow execution method to initiate execution of the handler method.

Abstract: The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (100, 1000), in one embodiment without limitation, includes a dielectric layer (120, 1020) located over a wafer substrate (110, 1010), and a semiconductor substrate (130, 1030) located over the dielectric layer (120, 1020), the semiconductor substrate (130, 1030) having one or more transistor devices (140, 1040) located therein or thereon. The integrated circuit (100, 1000) may further include an interconnect (170, 1810) extending entirely through the semiconductor substrate (130, 1030) and the dielectric layer (120, 1020), thereby electrically contacting the wafer substrate (110, 1010).

Abstract: An amplifier system may include an output stage configured to provide an amplified output signal at an output thereof based on an input signal, the output stage being connected between first and second supply voltages. A dynamic power supply control system provides the first and second supply voltages, the dynamic power supply being configured to adjust the first and second supply voltages as a function of the input signal such that a difference between the first and second supply voltages remains substantially constant.

Abstract: A packaged integrated circuit (IC) (100) includes a first substrate (110) including a first plurality of layers and first circuit coupling features (112) at an upper surface of the first substrate (110). The first plurality of layers include a first electromagnetic interference shielding layer (132). The packaged IC also includes a second substrate (106) having an upper surface attached to a lower surface of the first substrate (110) by an electrically conductive adhesive material (136). The second substrate (106) includes a second plurality of layers and a second circuit coupling feature (108) at a lower surface of the second substrate (106). The first plurality of layers includes a second EMI shielding layer (134). The packaged IC further includes a functional die (124) disposed between the first (110) and the second (106) substrates and functionally coupled to the first (112) and/or the second (108) circuit coupling features.

Abstract: An equalization circuit that allows particularly for lowpass filtering by transmission lines comprises a compensating equalizer controlled according to whether the edges between bits in the data waveform are early or late. Adjusting the equalization causes edges to appear in the same place, whereas if the adjustment is incorrect certain edges will be late and certain edges will be early depending on the history of “1”s and “0”s in the data stream. This is an effect of so-called intersymbol interference. The control mechanism includes circuits for recognizing patterns of “1”s and “0”s in the recent history of the data waveform whose occurrence is used to trigger the adjustment of the equalizer.

Abstract: A method of forming an interconnect structure for an integrated circuit, including the steps of providing a substrate and forming a dielectric stack on the substrate including an etch-stop layer, a low-k dielectric layer, and a hardmask layer. The method further includes the steps of patterning a photoresist masking layer on the dielectric stack to define a plurality of feature defining regions and plasma processing the substrate in a plasma-based reactor, The processing step includes etching a plurality of features into the hardmask layer and at least a portion of the low-k dielectric layer and performing a plasma treatment process in situ in the plasma-based reactor, where the plasma treatment process includes flowing at least one hydrocarbon into the reactor and generating a plasma, where a mass flow rate of the hydrocarbon is at least 0.1 sccm. The method also includes forming a metal conductor in the plurality of features.

Abstract: A method for changing an effective capacitance of an amplifier circuit having a match transistor and a coupled cascode transistor includes changing an on-state of at least one of a plurality of sub-transistors of the match transistor. The method further includes changing a transconductance of the match transistor as a function of the change of the on-state. The method further includes changing an equivalent resistance, as measured between a source and a drain of the cascode transistor, as a function of the change of the transconductance of the match transistor.

Abstract: A system and method for a die-to-die interconnect interface and protocol for stacked semiconductor dies. One preferred embodiment comprises an integrated circuit (IC) package comprising a first semiconductor die that includes an interface to a memory-mapped device, a second semiconductor die that does not include an interface to a memory mapped device, and a data bus coupling the first semiconductor die to the second semiconductor die (the data bus used to transfer a control word and a data word). The control word comprises a data word start address that corresponds to a location in the memory-mapped device. The data word is transferred from the second semiconductor die to the first semiconductor die and is stored by the first semiconductor die at the location in the memory-mapped device. Both semiconductor dies are mounted within the IC package.

Abstract: An interference interlock between leadframe features and a mold compound is provided in a packaged semiconductor device by exposing at least one predetermined surface area to an etching process prior to a molding step. This produces an etched recess with a recessed wall delimited by a step wall, generally perpendicular and adjacent to the recessed wall. The step wall is partially undercut by etching. During the molding step, the recessed wall and the step wall are both contacted by and embedded in the molding compound.

Abstract: System and method for utilizing two prisms spatially separated is provided. The two prisms spatially separated allows the two prisms typically found in a TIR optical relay system to be spatially separated. In an embodiment, one or more optical relay lenses are interposed between the two prisms. The prism positioned on the object side may be integrated into one or more of the optical relay lenses, thereby further simplifying the optical relay design. In another embodiment, the one or more optical relay lenses may have an optical axis that is offset from the optical axis of incoming light to cause a pupil shift. An aspherical lens may be included to correct for the pupil shift and create a more uniform illumination image.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes a write transistor gated by a write word line. The circuitry also includes a read buffer circuit coupled to the SRAM cell core to read the cell without disturbing the state of the cell. The read buffer circuit includes a read transistor gated by a read word line, the read transistor coupled between a read bit-line and a read driver transistor that is further coupled to a voltage source Vss. The read driver transistor and a first driver transistor of the cell core are both gated by one output of the cell core. The read transistor has an electrical characteristic that differs from that of the core cell first driver transistor.

Abstract: This invention is a new approach for the image watermarking in the wavelet transform domain based on sequency of the host and watermark image. For each sub-band a first transform level of the host image is thresholded and binarized. Sequencies of thresholded and binarized data host image are compared with sequencies of the discrete wavelet transformed watermark image to form a watermarking sequency mask. The watermarked wavelet domain data is formed by combining data elements of the discrete wavelet transformed host image with corresponding data elements of the wavelet transformed watermark image as filtered by the watermarking mask. A reverse process can extract the watermark with a high degree of accuracy even after attack upon the watermarked host image.

Abstract: A detector and detection method for identifying unknown chemical solutions following chemical spills includes a specific gravity detector including a detector column having an inlet end operable to collect a sample of a solution, wherein the detector column is formed of an optically transparent material to allow visual observation of the sample in the detector column. At least a first plurality of specific gravity floats including a first specific gravity float is located and moveable within the detector column, wherein the first specific gravity float has a density to float in liquids having a specific gravity of greater than a first density level. At least a second specific gravity float is located and moveable within the detector column, wherein the second specific gravity float has a density to float in liquids having a specific gravity greater than the first density level. A sample of an unknown solution from a site of a chemical spill is introduced into the detector column.

Abstract: In accordance with one embodiment of the present disclosure, a semiconductor substrate includes complementary metal-oxide-semiconductor (CMOS) circuitry disposed outwardly from the semiconductor substrate. An electrode is disposed outwardly from the CMOS circuitry. The electrode is electrically coupled to the CMOS circuitry. A resonator is disposed outwardly from the electrode. The resonator is operable to oscillate at a resonance frequency in response to an electrostatic field propagated, at least in part, by the electrode.

Abstract: A delay cell with a wider delay range is provided. The delay cell employs frequency dependent current source to generate the majority of the delay of the cell, while a control circuit (which is generally a current source that is controlled by a control voltage) provides additional delay. Thus, the delay cell provided here can be used to improve the performance of delay locked loops (DLLs) and other circuits.

Abstract: According to one embodiment of the present invention a method for capturing images on a screen is disclosed. The method includes directing light from a surface of a spatial light modular to an image field using a projection system; capturing light from the image field using the projection system, the projection system directing at least a portion of the captured light to the spatial light modulator; and directing at least a portion of the received captured light to an image capture system using the spatial light modulator.

Abstract: A method is provided of forming a semiconductor device. A substrate is provided having a dielectric layer formed thereover. The dielectric layer covers a protected region of the substrate, and has a first opening exposing a first unprotected region of the substrate. A first dopant is implanted into the first unprotected region through the first opening in the dielectric layer, and into the protected region through the dielectric layer.

Abstract: A method and apparatus for automatic white balancing of an image. The method includes retrieving scene analysis of the image, determining at least one of the type of the scene and a scene content map utilizing the scene analysis of the image, performing scene adaptive white balance, if overall scene category type is used, perform white balance by applying global R, G, B gains optimized for the global scene type, and if scene segmentation map is used, perform locally adaptive white balance by applying an R, G, B gain map optimized for each scene content.

Abstract: A stable, high-speed, high-efficiency constant voltage is provided without a complicated, large-scale, high-cost phase compensation circuit over a wide range of operating conditions. This voltage buck-boost switching regulator consists of a pair of voltage reducing transistors, a pair of voltage boosting transistors, inductance coil, output capacitor and controller. The controller has the following parts for performing PWM control of constant voltage for voltage reducing transistors and voltage boosting transistors: an output voltage feedback circuit, an inductor current sense circuit, a variable sawtooth wave signal generator, switching controllers, and a voltage boosting driver.