Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.

Abstract: In applications that use fractional-N phase locked loops (PLLs), the use of spread spectrum clocking (SSC) to reduced electromagnetic interference (EMI) would be desirable, but conflicts can occur. Here, a circuit is provided that includes both fractional logic circuitry and spread spectrum logic circuitry. This logic circuitry operates in combination with a phase selector to generally ensure that the likelihood of conflicts (which can occur in conventional circuit) are reduced.

Abstract: Pipe defects in n-type lightly doped drain (NLDD) regions and n-type source/drain (NDS) regions are associated with arsenic implants, while excess diffusion in NLDD and NSD regions is mainly due to phosphorus interstitial movement. Carbon implantation is commonly used to reduce phosphorus diffusion in the NLDD, but contributes to gated diode leakage (GDL). In high threshold NMOS transistors GDL is commonly a dominant off-state leakage mechanism. This invention provides a method of forming an NMOS transistor in which no carbon is implanted into the NLDD, and the NSD is formed by a pre-amorphizing implant (PAI), a phosphorus implant and a carbon species implant. Use of carbon in the NDS allows a higher concentration of phosphorus, resulting in reduced series resistance and reduced pipe defects. An NMOS transistor with less than 1·1014 cm?2 arsenic in the NSD and a high threshold NMOS transistor formed with the inventive method are also disclosed.

Abstract: An integrated stacked capacitor comprises a first capacitor film (46) of polycrystalline silicide, a second capacitor film (48) and a first dielectric (26) sandwiched between the first capacitor film (46) and second capacitor film (48). A second dielectric (34) and a third capacitor film (50) are provided. The second dielectric (34) is sandwiched between the second capacitor film (48) and third capacitor film (50). A method for fabrication of an integrated stacked capacitor comprises the following sequence of steps: applying a polysilicide layer (20) to form the first capacitor film (46); applying a first dielectric (26); applying a first metallization layer (28) to form the second capacitor film (48); applying a second dielectric (34); and applying a second metallization layer (44) to form the third capacitor film (50).

Abstract: A content-dependent scan rate converter with adaptive noise reduction that provides a highly integrated, implementation efficient de-interlacer. By identifying and using redundant information from the image (motion values and edge directions), this scan rate converter is able to perform the tasks of film-mode detection, motion-adaptive scan rate conversion, and content-dependent video noise reduction. Adaptive video noise reduction is incorporated in the process where temporal noise reduction is performed on the still parts of the image, thus preserving high detail spatial information, and data-adaptive spatial noise reduction is performed on the moving parts of the image. A low-pass filter is used in flat fields to smooth out Gaussian noise and a direction-dependent median filter is used in the presence of impulsive noise or an edge. Therefore, the selected spatial filter is optimized for the particular pixel that is being processed to maintain crisp edges.

Abstract: The present disclosure describes methods and systems for tiling video or still image data. At least some preferred embodiments include a method for accessing data that includes partitioning a display of graphical data into a plurality of two-dimensional tiles; mapping a two-dimensional tile of the plurality of two-dimensional tiles to a single memory row within a memory; and maintaining the graphical data for the two-dimensional tile in the single memory row.

Abstract: A high voltage field effect transistor device is fabricated. A substrate is provided. Isolation structures and well regions are formed therein. Drain well regions are formed within the well regions. An n-type channel stop resist mask is formed. N-type channel stop regions and n-type surface channel regions are formed. A p-type channel stop resist mask is formed. P-type channel stop regions and p-type surface channel regions are then formed. A dielectric layer is formed over the surface channel regions. Source regions are formed within the well regions. Drain regions are formed within the drain well regions. Back gate regions are formed within the well regions. Top gates are formed on the dielectric layer overlying the surface channel regions.

Abstract: An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.

Abstract: A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD™) 940, which make repeated contact between moving parts, require lubrication in order to prevent the onset of stiction (static friction) forces significant enough to cause the parts to stick irreversibly together, causing defects. These robust and non-corrosive fluorosurfactants 42, which consists of a hydrophilic chain 40 attached to a hydrophobic fluorocarbon tail 41, are applied by nebulization and replace the more complex lubricating systems, including highly reactive PFDA lubricants stored in polymer getters, to keep the parts from sticking. This lubrication process, which does not require the use of getters, is easily applied and has been shown to provide long-life, lower-cost, operable MEMS devices.

Abstract: A system for, and method of, enhancing I2C bus data rate and an electronic assembly including the system or the method. In one embodiment, the system includes: (1) a modulus register associable with a slave device and configured to contain a modulus and (2) data transfer logic associated with the modulus register and configured to transfer data from at least one memory location in the slave device to the I2C bus based on the modulus and a starting address and at least one acknowledgement signal received via the I2C bus.

Abstract: The present invention relates to an outer dome configured to provide protection and optical correction to a system of projection optics and the output thereof. More particularly, an optical projection system having an optical offset of greater than 100% is comprised within a projector housing having an outer dome comprised of an optically active material mounted onto an opening approximately coinciding with the optical projection system's exit pupil. The outer dome is configured to be decenterized from the exit pupil (e.g., the center of the dome is offset from the exit pupil in one or more of an x, y, and z direction) such that it provides optical correction to a projected image. Therefore, an outer dome is configured to provide protection to optical elements provided therein and improvement of projected image quality (e.g., reduced image distortion, reduced aberration).

Abstract: An RFID transponder is provided which includes an automatic gain control (AGC) stage for amplifying a radio frequency (RF) signal and for providing an amplified RF signal. The AGC stage has a control signal indicating an increase of the amplitude of the RF signal. A demodulator is coupled to receive the amplified RF signal for demodulating the amplified RF signal. The demodulator provides a data signal. A burst detector is coupled to receive the control signal of the AGC stage and adapted to provide a start signal in response to a change of the control signal. A wake pattern detector is coupled to receive the data signal and the start signal. The wake pattern detector is adapted to detect a predefined wake pattern in the data signal after having received the start signal and to issue a wake signal if the predefined wake pattern is detected for switching the RFID transponder from a first operating mode into a second operating mode having higher power consumption than the first operating mode.

Abstract: A clock signal generator (1) includes a phase locked loop (PLL) circuit (25) which requires a reference clock signal of at least a predetermined first frequency (fDIGCLK). A first clock signal (REFCLK) of a second frequency (fREF) that is substantially lower than the first frequency (fDIGCLK) is multiplied so as to produce a second clock signal (DIGCLK) which has a frequency at least as high as the first frequency (fDIGCLK) and which is phase-locked with respect to the first clock signal (REFCLK). The second clock signal (DIGCLK) is applied to a reference signal input of the PLL circuit (25), which produces an output clock signal (PLLCLK or CLKOUT).

Abstract: The present invention provides a method for manufacturing an integrated circuit. In one embodiment, the method includes etching one or more openings within a substrate using an etch tool, and subjecting the one or more openings to a post-etch clean, wherein a delay time exists between removing the substrate from the etch tool and the subjecting the one or more opening to the post-etch clean. This method may further include exposing the substrate having been subjected to the post-etch clean to a rinsing agent, wherein a resistivity of the rinsing agent is selected based upon the delay time.

Abstract: An exemplary system and methods implementing pulse width control in SRAM bit cell arrays that vary in size are described.

Abstract: A hybrid analog to digital converter circuit for a feedback input to a digital controller of a power supply includes a high resolution, analog to digital converter circuit in communication with a voltage error signal. The high resolution analog to digital converter circuit is configured to provide a first correction signal to the digital controller when the voltage error signal is within a first error range. The hybrid analog to digital converter circuit also includes at least one flash analog to digital converter circuit in communication with the voltage error signal. The flash analog to digital converter circuit(s) is configured to provide at least a second correction signal to the digital controller when the voltage error signal is within at least a second error range.

Abstract: A differential amplifier (10-1,2) includes an input stage (7) including first (M1) and second (M2) input transistors and first (4A) and second (4B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first (12) and second (13) conductors to the first and second load devices, respectively. Common mode feedback circuitry (6A) including first (M3), second (M4), and third (M5) transistors is combined with offset correction circuitry (8) including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (11). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (VOCM) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

Abstract: An operational amplifier (1B) amplifies an input signal (Vin) to produce an output signal (Vout), and includes a 3-stage amplifier (1C) including a first amplifier stage (2) receiving the input signal, a second amplifier stage (3) driven by the first amplifier stage (2), and a third amplifier stage (4) driven by the second amplifier stage to produce the output signal. A slew detection current (Idetect) is generated when the input signal (Vin) exceeds a certain magnitude, and is converted to a control signal (41) that operates a switch (MN0) to short-circuit output conductors of the first amplifier stage to prevent signal charge from building up on capacitances associated with the output of the first amplifier stage during slewing. The three stage amplifier can be a chopper-stabilized, notch-filtered amplifier.

Abstract: A method of communicating data across a channel that experiences near-end cross talk (NEXT) interference and far-end cross talk (FEXT) interference in alternate intervals. In one embodiment, a first data rate is determined for a first carrier-number mode that is to utilize a first bit table, a second data rate is determined for a second carrier-number mode that is to utilize dual bit tables, a third data rate is determined for a third carrier-number mode that is to utilize a second bit table during a FEXT interval, and a modem is configured to transmit using the mode having a highest data rate.

Abstract: An apparatus is provided to determine pre-distortion for a nonlinear system. The apparatus comprises a datapath and a power amplifier. The datapath employs predistortion data to generally linearized the power amplifier. To generate this predistortion data, an indirect learning circuit and a direct learning circuit can be employed. The indirect learning circuit is generally coupled to the amplifier circuit so that it can iteratively adjust predistortion data during an indirect learning mode until convergence is reached. The direct learning circuit is generally coupled to the amplifier circuit and the indirect learning circuit and that receives the input signal so that the predistortion data can be copied to the direct learning circuit from the indirect learning after convergence is reached and so that the direct learning circuit can adjust the predistortion data during a direct learning mode.