Abstract: While PC trace is on, and the trace is in predication or general event profiling mode, trace hardware captures events in each cycle. Trace hardware inserts this information into data logs, and does a right shift to compact the data. The trace window will eventually close, either because tracing has been turned off, or because a periodic sync point is generated to reset the window. In either of these two cases, the data log may be incomplete, fully packed, or just overflow into the next packet. An index is generated pointing to the last valid location in the data log in order to save transmission bandwidth.

Abstract: In an apparatus and method for monitoring defects in wafers, a monitoring circuit is fabricated on an area of each one of the wafers. The monitoring circuit includes representative devices that replicate similar devices located in a die area of the wafers. Defects if present in the representative devices contribute to a generation of a noise, thereby causing an imbalance in a differential signal measurable across selected ones of the representative devices. A digitizing circuit that uses a common mode voltage as a reference to measure the imbalance digitizes the differential signal to a digital signal, the digital signal being indicative of the noise generated by the defects. The digital signal is stored over a configurable time interval to form a digital bit stream. The digital bit stream is compared to a reference to determine whether the defects are within an allowable range.

Abstract: Delay lock loop circuits are described, which may include two or more delay stages that each includes a plurality of selectable delay elements. A reference signal drives an input of the first delay stage, which provides a first output. The first output drives an input of the second delay stage, which provides a second output. The circuits further include a first selector register that is associated with the first delay stage. A value maintained in the first selector register determines a number of the selectable delay elements utilized in the first delay stage. The circuits further include a second selector register associated with the second delay stage. A value maintained in the second selector register determines a number of the selectable delay elements utilized in the second delay stage. Modification of the values maintained in the first and second selector registers are synchronized to the first and second outputs, respectively.

Abstract: A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric layer on the semiconductor surface and a polysilicon layer on the gate dielectric layer. The polysilicon layer is patterned while being undoped to form a plurality of polysilicon comprising gates. A first pattern is used to protect a plurality of PMOS devices and a first n-type implant is performed to dope the gates and source/drain regions for a plurality of NMOS devices. A second pattern is used to protect the PMOS devices and the sources/drains and gates for a portion of the plurality of NMOS devices and a second n-type implant is performed to dope the gates of the other NMOS devices.

Abstract: A software pipelined loop tracing method involves inhibiting an output of trace data at a start of a software pipelined loop (SPLOOP). A skip in an output trace packet is indicated if the SPLOOP is skipped, and the SPLOOP is indicated at a cycle of an epilog state in the output trace packet if the SPLOOP is not skipped. An iteration count indication SPLOOP information and a position within a SPLOOP, is maintained. A periodic SPLOOP marker (PerSP) coinciding with a sync point is output if the SPLOOP is active.

Abstract: Provided are a system and method for reducing failures due to hinge memory. The method, in one embodiment, includes providing a torsional element having an amount of hinge memory, wherein the hinge memory is at least partially created using an average operational temperature. The method, in this embodiment, further includes subjecting the torsional element having the hinge memory to a temperature equal to or greater than the average operational temperature while the torsional element is in a parked state for an amount of time to reduce the amount of the hinge memory.

Abstract: Methods and apparatus for a self-tracking high-side pre-driver control are described. In an example, a method is described comprising charging a first terminal associated with a first capacitive element to a first voltage with respect to ground and a second terminal associated with a second capacitive element to a second voltage with respect to ground, changing the first voltage and the second voltage with respect to ground by changing a swing voltage, selecting one of the first voltage or the second voltage based on a first switched-mode power supply topology or a second switched-mode power supply topology and driving a transistor using the selected voltage.

Abstract: An illumination source and a method therefor. A light source includes a light circuit configured to process light and direct light, and a lighting element optically coupled to the light circuit to provide multiple colors of light. The light circuit propagates light using light guides. The use of light guides eliminates the use of free space optical elements, enabling the creation of more compact light sources. Furthermore, the use of light guides may enable the creation of light sources with fewer mechanical restrictions, thereby making the light sources potentially more reliable and less expensive.

Abstract: Last stall information is transmitted if the last stall standing function is enabled, one of the stall elements was active during the last clock cycle, no stall condition exists during the current cycle and the stall threshold has been met. Last stall standing operation provides a label associated with each stall period that exceeds a specified threshold. This provides the means to filter out some stall bursts to reduce trace bandwidth.

Abstract: The objective of this invention is to perform high-precision tracking error detection and tracking control using digital circuitry at relatively low speed and with a small circuit scale. Tracking servo circuit is formed as a single-chip circuit. Low-pass filters (LPF) and gain control amplifiers (GCA) of the input portion are analog circuits, while the circuits after analog-digital (A/D) converters, that is, offset cancellation circuits, equalizers (EQ), first and second phase difference detectors, adder, low-pass filter (LPF), gain control amplifier (GCA), and servo DSP are all digital circuits.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: This invention is a method for speeding up block matching based motion estimation for video encoder. The invention 1) calculates statistics for a candidate motion vector for a predetermined fraction of the pixels of a macroblock, 2) makes an early decision based on this preliminary cost function, and 3) terminates the block matching process without calculating the cost function for other pixels if the preliminary cost function is not less than a predetermined threshold. This early decision for goodness estimation provides an economy of processing load when a large portion of data is left untouched (i.e. unprocessed). The present invention employs feedback control to reduce the predetermined threshold for quick convergence upon each detection of a better match.

Abstract: According to one embodiment of the present invention, a system for illuminating a target includes a light source configured to emit one or more light beams with a first divergence. The system further includes a lens separated from the light source. The lens is configured to substantially satisfy the sine condition without removing spherical aberrations from the one or more light beams. The lens is further configured to receive the one or more light beams with the first divergence. The lens is further configured to change the first divergence of the one or more light beams to a second divergence. The second divergence is less than the first divergence. The second divergence is greater than zero. The lens is further configured to transmit the one or more light beams with the second divergence.

Abstract: Conventional drivers for transducers oftentimes did not provide an efficient driving mechanism because the driving signal was not “close enough” to the natural frequency of the transducer. Here, a driver for a transducer is provided that measures the natural frequency of the transducer and generates a driving signal accordingly. Thus, a more efficient driver is provided.

Abstract: One embodiment of the present invention relates a method for preventing the formation of electrical opens due to localized copper dissolution during fabrication of metal interconnect wires. More particularly, a semiconductor body comprising one or more exposed copper metal levels is coated with a benzotriazole (BTA) solution. The semiconductor body is then dried, resulting in a protective layer of BTA coating the copper metal levels. The protective layer of BTA passivates the exposed copper surface by forming a protective BTA layer that prevents the copper metal level from coming into direct contact with deionized water thereby preventing copper metal dissolution and providing improved integrated chip yields and reliability.

Abstract: Command reordering in the hub interface unit (HIU) of Enhanced Direct Memory Access (EDMA) functions is described. Without command reordering in the EDMA, commands are issued by the HIU to the peripheral in order of issue. If the higher priority transfers are issued later by the EDMA, the previously issued lower priority transfers would block the higher priority transfers. Command reordering in the HIU causes transfers to be reordered and issued to the peripheral based on their priority. Reordering allows the EDMA and HIU to give due service to high priority transfer requests with decreased weight placed on the order in which the requests were issued.

Abstract: A system comprises a first processor, a second processor coupled to the first processor, an operating system that executes exclusively only on the first processor and not on the second processor, and a middle layer software running on the first processor and that distributes tasks to run on either or both processors. A synchronization unit coupled to the first and second processors also may be provided to synchronize the processors. Further still, a translation lookaside buffer may be included that is shared between the processors. Each entry in the translation lookaside buffer (“TLB”) may include a task identifier to permit the operating system or middle layer software to selectively flush only some of the TLB entries (e.g., the entries pertaining to only one of the processors).

Abstract: Bandwidth expansion for audio signals by frequency band translations plus adaptive gains to create higher frequencies; use of a common channel for both stereo channels limits computational complexity. Adaptive cut-off frequency determination by power spectrum curve analysis, and bass expansion by both fundamental frequency illusion and equalization.

Abstract: An integrated circuit is provided for scan driving that can significantly reduce the chip size. In first region AODD, odd-numbered output pads OUT1, OUT3, . . . OUT173, OUT175, driver circuits DR1, DR3, . . . DR173, DR175, and flip-flops SREG1, SREG3, . . . SREG173, SREG175 in an order corresponding to the order of the odd-numbered scanning lines are each arranged as a column in the X-direction, and, at the same time, output pads OUTi, driver circuits DRi and flip-flops SREGi corresponding to the scanning lines are arranged in the same row in the Y-direction (chip width direction). In second region AEVEN, even-numbered output pads OUT2, OUT4, . . . OUT174, OUT176, driver circuits DR2, DR4, . . . DR174, DR176, and flip-flops SREG2, SREG4, . . .

Abstract: Audio loudspeaker and headphone virtualizers and methods use room impulse responses with modified individual head-related transfer functions prior to superposition including middle truncation; and perform convolutions in the frequency domain with zero-padded sections to avoid circular convolution overlap.