Abstract: Power optimization in a medical implant based system. A method includes receiving a portion of a signal by a first transceiver. The method further includes determining, from the portion of the signal, a time duration after which a subsequent portion of the signal will be transmitted. The subsequent portion is transmitted at end of the portion. The method also includes entering into an inactive state for the time duration.

Abstract: A single poly EEPROM cell in which the read transistor is integrated in either the control gate well or the erase gate well. The lateral separation of the control gate well from erase gate well may be reduced to the width of depletion regions encountered during program and erase operations. A method of forming a single poly EEPROM cell where the read transistor is integrated in either the control gate well or the erase gate well.

Abstract: The present application describes a method and system for discovering and authenticating communication devices within a wireless network. According to an embodiment, communication devices exchange public keys using multiple messages each including at least a portion of the public key of the sending device. The devices authenticate the receipt of the public key and establish a shared master key. The shared master key is used to further derive a session key for securing the application data between the communicating devices for a current session.

Abstract: The present invention provides methods and apparatus for adjusting the resonant frequency, scan velocity or other parameters of a pivotally functional surface such as an oscillating mirror used as the scanning engine of a laser printer or projection display. The selected parameter is adjusted by the application of tensional or compression stress to the torsional hinges of the mirror. According to one embodiment, the appropriate stress is generated by a slice of piezoelectric material bonded to the mirror device itself or to other portions of the support structure of the scanning engine.

Abstract: A power switching circuit in CMOS technology has a power MOS transistor and a driver stage. The power MOS transistor is operated at a higher supply voltage in excess of its maximum allowable gate-source voltage; and the driver stage of the level shifter is operated at a lower supply voltage substantially lower than the supply voltage for the power MOS transistor. The driver stage includes a pair of driver MOS transistors coupled in series between a higher supply voltage rail and a reference potential rail, and at an interconnection node coupled to the gate of the power MOS transistor. The gates of the driver MOS transistors are AC-coupled to drive signals of mutually opposite phase; and the gates of the driver MOS transistors are each connected to the higher voltage supply rail through a respective parallel connection of a first resistor and a second resistor connected in series with a non-linear component.

Abstract: A method is provided for writing to a memory cell having a read access circuit that is separate and isolatable from a write access circuit. The method comprises providing a logic state to be written to the memory cell onto a write bit line coupled to the memory cell through the write access circuit, changing a write word line that controls the write access circuit from a deactivated low voltage state to an activated high voltage state, and changing a read word line that controls the read access circuit from an activated low voltage state to a deactivated high voltage state, wherein the change in voltage on the read word line provides a voltage boost to the voltage on the write word line caused by the electrical coupling between the read word line and the write word line to provide write assist to the memory cell during a write operation.

Abstract: The present invention relates to an electronic transmitter for serially transmitting bit sequences. The electronic transmitter includes a detection device 10 and a transmitting device 12. The detection device 10 is adapted to detect a predefined bit sequence for transmittal. The predefined bit sequence is susceptible to inter-symbol-interference. The transmitting device 12 is adapted to transmit serially the detected predefined bit sequence in such a way, that a duration for transmittal of a particular bit in said predefined bit sequence is longer than a duration of transmittal of remaining bits in said predefined bit sequence.

Abstract: Embodiments of the invention provide method and apparatus for generating a structure in an orthogonal frequency division multiplexing OFDM communication system having a transmitter with one or more transmitting antennas. The method includes composing a frame with a time domain and a frequency domain. The frame has a transmission time interval in the time domain and occupies a bandwidth in the frequency domain. The transmission time interval has multiple orthogonal frequency division multiplexing symbols. A pilot signal is located from a transmitting antenna into two non-consecutive orthogonal frequency division multiplexing symbols of the frame.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A method and apparatus of an adaptive gain control (AGC) unit. The method includes receiving a noisy input signal and determining to utilize a stethoscope in at least one of a noise suppression mode or in amplification mode depending if the noise level is at least one of above or below a threshold, wherein the stethoscope is in noise suppression mode when K is less than the threshold and is amplification mode when K is above the threshold.

Abstract: In a lithography process using an ultraviolet process, the applied ultraviolet resist can be removed by intentionally condensing the ultraviolet resist before removing the ultraviolet resist.

Abstract: A process of polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation and then removing power from the integrated circuit. A process polarizing a programmable data storage component of an integrated circuit by polarizing the ferroelectric capacitors in the same orientation, then removing power from the integrated circuit. A process of polarizing a programmable data storage component of an integrated circuit by polarizing corresponding ferroelectric capacitors in same orientations, then removing power from the integrated circuit. An integrated circuit containing a programmable data storage component and a ferroelectric capacitor polarization circuit that is configured to polarize a first data ferroelectric capacitor and a second data ferroelectric capacitor in desired polarization configurations by applying biases to a first state node, a second state node, a first plate node, and a second plate node.

Abstract: A synchronous rectifier is switched in accordance with a primary switch transition and a reference signal representing current in a current storage device to which the synchronous rectifier is coupled. A current emulator provides a signal representing current in the current storage device as a volt-second product so that current stored in the current storage device while the primary switch is on is discharged by the synchronous rectifier. The use of a current emulator provides an inexpensive solution for controlling synchronous rectifier transitions without resorting to more expensive current sensing solutions that are commercially impracticable. Blanking intervals are provided for avoiding false transitions of the synchronous rectifier when the primary switch turns on and after the synchronous rectifier turns off. The disclosed system and method can be applied to flyback converters for a synchronous rectifier on the secondary side of a transformer, or the inductor of buck converters.

Abstract: A coordinated multipoint transmitter is for use with a network MIMO super-cell and includes a coordination unit configured to provide joint link processing to coordinate a multipoint transmission corresponding to a set of transmission points. Additionally, the coordinated multipoint transmitter also includes a transmission unit configured to transmit the multipoint transmission using the set of transmission points. Additionally, a coordinated transmission receiver is for use with a network MIMO super-cell and includes a reception unit configured to receive a multipoint transmission corresponding to a set of transmission points. The coordinated transmission receiver also includes a processing unit configured to process the multipoint transmission from the set of transmission points.

Abstract: An electronic device is provided for analog to digital conversion using successive approximation. The device comprises a first ADC stage. The first ADC stage includes a first plurality of capacitors adapted to sample an input voltage, and adapted to be coupled to either a first reference signal level or a second reference signal level. At least one capacitor of the first plurality of capacitors is adapted to be left floating. A control stage is adapted to switch the at least one floating capacitor to the first reference signal level or the second reference signal level in response to an analog to digital conversion decision made by a second ADC stage.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.