Abstract: A method for forming carbon-doped epitaxial SiGe of a PMOS transistor by providing a semiconductor substrate having a PMOS transistor gate stack and recess etched active regions. The method includes forming carbon-doped epitaxial SiGe within the recess etched active regions. A PMOS transistor includes a semiconductor substrate, a PMOS transistor gate stack, and source/drain extensions. The PMOS transistor also includes carbon-doped epitaxial SiGe source/drain regions.

Abstract: In recent years, the performance of CMOS and CCD image sensors has dramatically improved, and to utilize the improved performance of these sensors, processing circuitry is provided here. This processing circuitry employs a adjustable gain that varies depending on the intensity of the signal from the image sensor so as to reduce noise, reduce area used, and reduce power consumption.

Abstract: A method for making a transistor 20 that includes using a transition metal nitride layer 200 and/or a SOG layer 220 to protect the source/drain regions 60 from silicidation during the silicidation of the gate electrode 90. The SOG layer 210 is planarized to expose the transition metal nitride layer 200 or the gate electrode 93 before the gate silicidation process. If a transition metal nitride layer 200 is used, then it is removed from the top of the gate electrode 93 before the full silicidation of the gate electrode 90.

Abstract: A method for setting a periodicity and an offset in rank indicator (RI) reporting in a user equipment in a wireless communication system receives a radio resource control (RRC) signal from a base station, decodes a RI periodicity and offset configuration index, sets the periodicity and offset in accordance with said decoded periodicity and offset configuration index and reports a RI according to the set periodicity and offset. The periodicity is an integer and reporting a RI reports with equal the product of the periodicity and a period of reporting of the channel quality indicator (CQI) and the preceding matrix indicator (PMI).

Abstract: An integrated circuit containing a vertical interconnect that includes a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure. An upper conductive structure contacts a top surface of the vertical interconnect. A process of forming an integrated circuit that includes forming a vertical interconnect that has a region of interconnect metal continuously surrounding one or more dielectric pillars. The vertical interconnect electrically contacts a top surface of a lower conductive structure, and an upper conductive structure contacts a top surface of the vertical interconnect.

Abstract: Authentication methods are provided that allow for superior security, power consumption, and resource utilization over existing authentication methods. By computing only two hashes of a shared secret password for each protocol run, the methods described in this disclosure dramatically reduce the computational power needed to perform authentication. Similarly, by exchanging these hashes bitwise or piecewise for verification, rather than performing new hashes including each bit of the password separately, the methods described in this disclosure reveal less information about the password being authenticated than existing methods. The methods described in this disclosure also allow for authentication using fewer messages and with lower latency, reducing the amount of operational power used in the authentication process.

Abstract: An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.

Abstract: In a method and apparatus for compensating non-linearity of a gain of a residual amplifier (RA), a pipelined analog-to-digital converter (ADC) converts an analog input to a digital output (DO). The ADC includes a plurality of pipelined stages (PPS). Each stage, which includes an instance of the RA, provides a digital code corresponding to an output of the RA included in a preceding stage. A memory stores a piecewise linear representation for modeling the non-linearity of the gain. A calibrated gain of the RA corresponding to each region of a plurality of linear operating regions of the RA is stored in the memory. A gain adjuster adjusts the digital code for each one of the PPS in accordance with a gain factor derived from the calibrated gain for each one of the PPS. A constructor constructs the DO from the adjusted digital code received from each one of the PPS.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: Synchronization circuitry and synchronization system for synchronizing converters/controllers that are electrically-coupled to a common synchronization node. The synchronization system includes synchronization circuitry, oscillation circuitry, and a leading edge detector and pulse generator. The synchronization circuitry includes pull-up circuitry and pull-down circuitry for generating a voltage pulse-train at the synchronization node. The oscillation circuitry controls which of the pull-up and the pull-down circuitry is driven ON and which is driven OFF.

Abstract: A low charge injection, low clock feed-through switch (1) has an input signal (Vin) applied both to the sources of first (S1) and second (2) switching transistors. A first clock signal (P) having pulses of a first duration ts is applied to a gate of the first switching transistor, and a second clock signal (Pcoarse) having pulses of a second duration m×ts substantially less than the first duration is applied to a gate of the second switching transistor. A capacitor (C) is charged toward the input voltage through both the first and second switching transistors during the pulse of the second clock signal. The capacitor is charged further toward the input voltage during a remaining portion of the pulse of the first clock signal.

Abstract: Systems and methods for determining coefficients of an Finite Impulse Response (FIR) filter are disclosed. The FIR filter coefficients are computed by determining a sine of an input value and an inverse of the input value. The sine of the input signal and the inverse of the input signal are multiplied together to form a sinc value of the input value. The sinc value is employed to determine the coefficient. The system and method can be repeated to compute any number of FIR filter coefficients in real-time. The sine of the input signal is computed utilizing a memory lookup table. The memory lookup table includes pairs of uniformly distributed values for the sine and cosine functions in the range of 0 to ?. The inverse of the input value is computed using an inverse memory lookup table, a most significant digit and a remainder. The coefficient is then computed from a product of the sine of the input signal and the inverse of the input signal.

Abstract: A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge pump receives control inputs from outputs of the phase frequency detector. Pulse duration detecting circuitry limits charge and discharge current pulses supplied to the loop capacitance by the charge pump to durations less than predetermined permissible durations.

Abstract: Multiple blanket implantations of one or more p type dopants into a semiconductor substrate are performed to facilitate isolation between nwell regions subsequently formed in the substrate. The blanket implantations are performed through isolation regions in the substrate so that the p type dopants are implanted to depths sufficient to separate the nwell regions. This increased concentration of p type dopants helps to mitigate leakage between the nwell regions as the nwell regions are brought closer together to increase packing densities.

Abstract: A method of capacitance-to-voltage conversion with an external sensor capacitor (CP) and a capacitance-to-voltage converter (14) implemented on an integrated readout circuit that includes a reference capacitor (CR), a sampling capacitor (CS) and a sampling amplifier (22) and which has input terminals (16) to which the sensor capacitor (CP) is connected. The method comprises the steps of a) applying a reference voltage (Vref) to the series connected sensor capacitor (CP) and reference capacitor (CR) and charging the sampling capacitor (CS) to the potential at the interconnection node (A) between the sensor capacitor (CP) and the reference capacitor (CR), b) connecting the sampling capacitor (CS) to inputs of the sampling amplifier.

Abstract: Provided in one embodiment is a heatsink. The heatsink may include a rib having first and second opposing surfaces. The heatsink may further include a first set of fins extending from the first surface, and a second set of fins extending from the second surface. The heatsink may further include one or more mounts configured to secure one or more solid state illumination sources to the rib.

Abstract: Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes detecting the predefined sequence by a second medical transceiver. The method also includes performing predetermined action if the predefined sequence is detected. In one example, the predetermined action includes determining presence of a signal.

Abstract: Polling mechanism in a medical implant based system. A method for operating a receiver includes searching for a signal by a receiver. The method further includes entering into an inactive state for a predefined time interval, if the signal is not detected. The method also includes altering at least one of sensitivity and the predefined time interval if number of times the searching is performed without detecting the signal exceeds a threshold. Moreover, the method includes searching for the signal with at least one of altered sensitivity and altered predefined time when the receiver enters into an active state.

Abstract: Parallel search circuit for a medical implant receiver. The circuit includes a radio frequency receiver that receives a first set of contents of a band of channels. The circuit also includes a processing circuit coupled to the radio frequency receiver to process in parallel a second set of contents of a plurality of channels of the band of channels and to detect a signal in the band of channels.

Abstract: Enabling non-interoperability among transceivers of devices. A method includes transmitting a signal at a predefined symbol rate by a first transceiver of a first device of a first plurality of devices. The predefined symbol rate is unique for each transceiver of each device of the first plurality of devices. The method also includes detecting the signal by a second transceiver of a second device of a second plurality of devices. The second transceiver has a symbol rate similar to the predefined symbol rate.