Patents Assigned to Texas Instruments
  • Patent number: 9513336
    Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: December 6, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9515059
    Abstract: A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound and forms walls rising from the frame of fingers to create an enclosed cavity for the LED. The pads, leads, and fingers connected to a board using a layer of solder for attaching the proximity sensor.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: December 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andy Quang Tran, Lance Wright
  • Patent number: 9516663
    Abstract: Transmission of information in a wireless network is performed by allocating a channel from a transmitter to a receiver. The channel has at least one time slot with each time slot having a plurality of symbols. Each slot contains at least one reference symbol (RS). As information becomes available for transmission, it is classified as prioritized information (PI) and other information. One or more priority symbols are generated using the digital samples of the priority information. Other symbols are generated using the other data. Priority symbols are transmitted on the channel in a manner that separation of priority symbol(s) and a reference symbol does not exceed a time duration of one symbol. For example, Rank Indicator (RI) is transmitted using symbol k, ACKNAK is transmitted using symbol k+1; and the reference signal (RS) is transmitted using symbol k+2, wherein symbols k, k+1, and k+2 are consecutive in time. The other symbols are transmitted in available locations.
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: December 6, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Tarik Muharemovic, Zukang Shen, Pierre Bertrand, Eko Nugroho Onggosanusi
  • Publication number: 20160349774
    Abstract: Dynamic biasing circuits for low drop out (LDO) regulators are described. In some embodiments, an electronic circuit may include a low drop out (LDO) regulator; and a biasing circuit coupled to the LDO regulator, the biasing circuit configured to: monitor a first electrical current and a second electrical current; select a greater of the first or second electrical currents; and provide the selected electrical current to the LDO regulator. In other embodiments, a method may include: providing a digital core and a low drop out (LDO) regulator coupled to the digital core, wherein the digital core is configured to operate in an active mode and in a standby mode; monitoring, via a current selector circuit coupled to the LDO regulator, a first current and a second current; selecting a greater of the first or second electrical currents; and providing the selected current as a biasing current to the LDO regulator.
    Type: Application
    Filed: November 3, 2015
    Publication date: December 1, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sri Navaneethakrishnan Easwaran, Vijayalakshmi Devarajan
  • Publication number: 20160352508
    Abstract: Plaintext analysis as a countermeasure against side channel attacks. A system is disclosed that includes an encryption/decryption module performing an encryption algorithm for encrypting plaintext data using a secure encryption key stored in non-volatile memory coupled to the encryption/decryption module, the encryption/decryption module further performing an algorithm for decrypting encrypted ciphertext using the secure encryption key; and a plaintext analysis module coupled to the plaintext data, the plaintext analysis module performing an analysis and determining whether the plaintext data correlates to expected plaintext data, the plaintext analysis module outputting a signal indicating a side channel attack, responsive to the determining. Additional methods and apparatus are disclosed.
    Type: Application
    Filed: November 3, 2014
    Publication date: December 1, 2016
    Applicant: Texas Instruments Deutschland GMBH
    Inventors: Oscar Miguel Guillen-Hernandez, Ralf Brederlow
  • Publication number: 20160351508
    Abstract: Systems and methods for creating unique device identification for semiconductor devices are described. In some embodiments, a method may include receiving a wafer identification mark printed on a semiconductor wafer having a plurality of dies fabricated thereon; receiving a leadframe identification mark printed on a leadframe configured to receive the plurality of dies during a die attach operation; and for each of the plurality of dies: (a) recording a wafer location of a given die prior to the die attach operation; (b) recording a leadframe location of the given die after the die attach operation; (c) creating a device identification mark for the given die based upon the wafer identification mark, the leadframe identification mark, the wafer location, and the leadframe location; and (d) printing the device identification mark on a package of the given die.
    Type: Application
    Filed: December 16, 2015
    Publication date: December 1, 2016
    Applicant: Texas Instruments Incorporated
    Inventors: Venkataramanan Kalyanaraman, Kalyan C. Cherukuri, Kenneth M. Butler
  • Patent number: 9509945
    Abstract: A data stream that contains periodic time reference values referenced to a first reference clock is received for transcoding. The received data stream is processed to form an output data stream that contains the periodic time reference values. At least one of the periodic time reference values is adjusted by adding a count value to the at least one periodic reference value to form an adjusted periodic time reference value. The output data stream is transmitted with the adjusted periodic time reference value.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yusuke Minagawa, Satoru Yamauchi
  • Patent number: 9510139
    Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment using M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK. Also, the PHY layer uses a constant symbol rate for BAN packet transmissions.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anuj Batra, Timothy M. Schmidl, Srinath Hosur, June Chul Roh
  • Patent number: 9508708
    Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kamel Benaissa
  • Patent number: 9506985
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: November 29, 2016
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9508601
    Abstract: An integrated circuit with an MOS transistor abutting field oxide and a gate structure on the field oxide adjacent to the MOS transistor and a gap between an epitaxial source/drain and the field oxide is formed with a silicon dioxide-based gap filler in the gap. Metal silicide is formed on the exposed epitaxial source/drain region. A CESL is formed over the integrated circuit and a PMD layer is formed over the CESL. A contact is formed through the PMD layer and CESL to make an electrical connection to the metal silicide on the epitaxial source/drain region.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kwan-Yong Lim, James Walter Blatchford, Shashank S. Ekbote, Younsung Choi
  • Patent number: 9506882
    Abstract: A system for processing real-time fluoroscopy image sequences. A first image frame is loaded into an upper level memory of a hierarchical memory system that is coupled to at least one processing core. The first image frame is processed with an object detection filter to form a likelihood image frame. The first image frame and the likelihood image frame is spatially filtered using a spatial filter look up table (LUT) stored in an L1 level memory of the processing core. The likelihood image frame is temporally filtering using a temporal filter LUT stored in the L1 level memory.
    Type: Grant
    Filed: January 18, 2012
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Udayan Dasgupta, Murtaza Ali
  • Patent number: 9509323
    Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.
    Type: Grant
    Filed: May 12, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Krishnaswamy Thiagarajan, Jagdish Chand Goyal, Srikanth Manian, Debapriya Sahu
  • Patent number: 9507600
    Abstract: A method and apparatus for executing program loops. A processor, includes an execution unit and an instruction fetch buffer. The execution unit is configured to execute instructions. The instruction fetch buffer is configured to store instructions for execution by the execution unit. The instruction fetch buffer includes a loop buffer configured to store instructions of an instruction loop for repeated execution by the execution unit. The loop buffer includes buffer control logic. The buffer control logic includes pointers, and is configured to predecode a loop jump instruction, identify loop start and loop end instructions using the predecoded loop jump instruction and pointers; and to control non-sequential instruction execution of the instruction loop. The width of the pointers is determined by loop buffer length and is less than a width of an address bus for fetching the instructions stored in the loop buffer from an instruction memory.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Christian Wiencke, Ralph Ledwa, Norbert Reichel
  • Patent number: 9507409
    Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Joel Martin Halbert, Vinay Agarwal
  • Patent number: 9508869
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Patent number: 9508633
    Abstract: A field-effect transistor package includes a leadframe with a first linear thickness (150a) and a leadframe pad (151) of a reduced thickness; a first terminal of a field-effect transistor chip (140) attached to the pad and a second and a third terminal remote from the pad; a metal sheet (110) of a second linear thickness (110a) connecting the second transistor terminal to a package terminal; a metal sheet (112) of a third linear thickness (112a) connecting the third transistor terminal to a package terminal; the sum of the first linear thickness (about 0.125 mm) and the second linear thickness (about 0.125 mm) plus attach material (about 0.05 mm) comprising the package thickness (about 0.3 mm).
    Type: Grant
    Filed: August 22, 2011
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Juan A. Herbsommer, Osvaldo J. Lopez, Jonathan A. Noquil
  • Patent number: 9510319
    Abstract: Several methods and systems for location estimation are disclosed. In an embodiment, the method includes performing a primary wireless scan to identify a first set of access points at a user location associated with a first user location estimate. A secondary wireless scan is performed at pre-defined time intervals subsequent to the primary wireless scan. A set of access points is identified corresponding to each secondary wireless scan. The method further comprises detecting a presence or an absence of user motion based on a number of shared access points between the first set of access points and a set of access points corresponding to each secondary wireless scan. A current user location is estimated to be the first user location estimate if the user motion is detected to be absent, or a second user location estimate computed based on geolocation signals if the user motion is detected to be present.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: November 29, 2016
    Assignee: Texas Instruments Incorporated
    Inventors: Sthanunathan Ramakrishnan, Sashidharan Venkatraman, Ravi Krishna Bhat, Jaiganesh Balakrishnan, Saket Thukral
  • Patent number: 9509325
    Abstract: The present disclosure describes a channel selector for use in an analog-to-digital converter that has a sampling circuit for converting an analog input to a digital output within a fault tolerance range. The channel selector includes a reception channel, a diagnostic channel, and an impedance compensator. The reception channel receives an analog signal for delivery to the sampling circuit when it is selected for coupling with the sampling circuit. The diagnostic channel receives a diagnostic signal for verifying the digital output of the sampling circuit when it is selected for coupling with the sampling circuit. The impedance compensator is configured to offset a high channel impedance of the reception channel based on the fault tolerance range of the sampling circuit and when the diagnostic channel is selected.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Timothy Paul Duryea, Vaibhav Garg
  • Patent number: 9510391
    Abstract: A method includes receiving a wireless beacon from an ad hoc network at a wireless device, wherein the wireless beacon includes a data structure that encodes at least a portion of a wireless identifier of an access point. The method includes configuring the wireless device from the data structure received from the wireless beacon. The method also includes establishing a wireless network between the access point and the wireless device utilizing at least a portion of the wireless identifier encoded in the data structure.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: November 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Avraham Baum, Artur Zaks, Ram Machness, Nir Nitzani