Abstract: An output voltage is compared to a reference voltage, comparison signals are generated, and control signals and mode signals are generated in response thereto. The output voltage is generated in response to the control signals. A speed of the comparing is increased in response to the mode signals indicating that the output voltage is being increased. The speed is reduced in response to the mode signals indicating that the output voltage is being reduced. For increasing the speed, a path is enabled to conduct current. While the path is enabled, at least one switched voltage is connected to vary an amount of the current conducted through the path. The switched voltage is at least one of the reference voltage and the output voltage. For reducing the speed, the path is disabled against conducting current. While the path is disabled, the switched voltage is disconnected from varying the amount.

Abstract: Embodiments of the invention provide a best-effort scheduled access method and system that enable nodes to request, and a hub to assign, tentative, but not committed, scheduled allocations, referred to as unscheduled bilink allocations, in which data traffic is transferred between the nodes and the hub on a best-effort basis. The tentative allocations will be available if the network of the hub still has enough bandwidth, but will be shifted or reduced otherwise. This invention unifies tentative and committed scheduled allocations in the same access framework, thereby facilitating access scheduling and offering access flexibility.

Abstract: A circuit assembly includes a substrate having a substrate electrical circuit, opposite top and bottom substrate surfaces, and a substrate hole extending through the substrate. The circuit assembly also includes a discrete component assembly electrically connected to the substrate electrical circuit and a support member attached to the discrete component. At least a portion of the discrete component is physically mounted in the substrate hole.

Abstract: An enhanced resolution successive-approximation register (SAR) analog-to-digital converter (ADC) is provided that includes a digital-to-analog converter (DAC), a comparator and enhanced resolution SAR control logic. The DAC includes analog circuitry that is configured to convert an M-bit digital input to an analog output. The comparator includes a plurality of coupling capacitors. The enhanced resolution SAR control logic is configured to generate an M-bit approximation of an input voltage and to store a residue voltage in at least one of the coupling capacitors. The residue voltage represents a difference between the input voltage and the M-bit approximation of the input voltage. The enhanced resolution SAR control logic is further configured to generate an N-bit approximation of the input voltage based on the stored residue voltage, where N>M.

Abstract: System, method, and device for maximizing brightness of solid-state illuminators while minimizing power usage based on individual scene contents. An embodiment varies power to each of the solid-state illuminators (red, green, & blue) based on the scene content that is being displayed optimizing the non-linear brightness response of solid-state illuminators.

Abstract: An integrated resonator apparatus includes a piezoelectric resonator and an acoustic Bragg reflector formed adjacent the piezoelectric resonator. The integrated resonator apparatus also includes a mass bias formed over the Bragg reflector on a side of the piezoelectric resonator opposite the piezoelectric resonator.

Abstract: Timely testing of die on wafer reduces the cost to manufacture ICs. This disclosure describes a die test structure and process to reduce test time by adding test pads on the top surface of the die. The added test pads allow a tester to probe and test more circuits within the die simultaneously. Also, the added test pads contribute to a reduction in the amount of test wiring overhead traditionally required to access and test circuits within a die, thus reducing die size.

Abstract: A method for derivation of a temporal motion data (TMD) candidate for a prediction unit (PU) in video encoding or video decoding is provided. The derived TMD candidate is for inclusion in an inter-prediction candidate list for the PU. The method includes determining a primary TMD position relative to a co-located PU in a co-located largest coding unit (LCU), wherein the co-located PU is a block in a reference picture having a same size, shape, and coordinates as the PU, and selecting at least some motion data of a secondary TMD position as the TMD candidate when the primary TMD position is in a bottom neighboring LCU or in a bottom right neighboring LCU of the co-located LCU, wherein the secondary TMD position is determined relative to the co-located PU.

Abstract: A method of encoding samples in a digital signal is provided that includes receiving a plurality of samples of the digital signal, and encoding the plurality of samples, wherein an output number of bits is adapted for coding efficiency when a value in a range of possible distinct data values of the plurality of samples is not found in the plurality of samples.

Abstract: The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.

Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation is treated as a cache miss to ensure that the requesting CPU will receive valid data.

Abstract: A metal oxide semiconductor field effect transistor (MOSFET) in and on a semiconductor surface provides a drift region of a first conductivity type. A plurality of active area trenches in the drift region, and first and second termination trenches are each parallel to and together sandwiching the active area trenches. The active area trenches and termination trenches include a trench dielectric liner and electrically conductive filler material filled field plates. A gate is over the drain drift region between active area trenches. A body region of a second conductivity abuts the active region trenches. A source of the first conductivity type is in the body region on opposing sides of the gate. A vertical drain drift region uses the drift region below the body region. A first and second curved trench feature couples the field plate of the first and second termination trench to field plates of active area trenches.

Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.

Abstract: The present disclosure relates to an apparatus comprising at least two operational amplifiers, a first and a second current input, at least one voltage output, and at least two resistors, wherein a first current source is connectable to the first current input, and a test current source is connectable to the second current input, and wherein the first current input is connected to an inverting input of the first operational amplifier and the second current input is connected to an inverting input of the second operational amplifier, and a first feedback resistor is connected between the output and the inverting input of the first operational amplifier and a second feedback resistor is connected between the output and the inverting input of the second operational amplifier, and wherein the voltage output is connected to the outputs of the first and the second operational amplifier.

Abstract: A multimedia system includes a processor coupled to a memory, a three-dimensional (3D) graphics engine to generate 3D graphics content, and a display controller to process and transport pixel data for transmission to a display via a display interface. Each of the processor, the 3D graphics engine, and the display controller accesses pixel data stored in the memory using a common decompression scheme. Additionally, each of the processor, the 3D graphics engine, and the display controller stores pixel data in the memory using a common compression scheme.

Abstract: An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.

Abstract: A Propagation Test instruction, a Decay Test instruction and a Cycle Test instruction provide testing of DC and AC interconnect circuits between circuits including JTAG boundary scan cells. A few additions to the Test Access Port circuitry, including gating producing a Capture Test Strobe (CTS) signal, and the boundary scan cells are required to implement the additional instructions. The instructions are extensions of the conventional JTAG operating structure.

Abstract: Systems and methods disclosed herein receive a network application proxy (NAP)-extended API function call issued by a networking-aware host application. The NAP-extended API function call provides parameter values associated with a host off-loadable packet exchange sequence. Using the parameter values, a NAP module intercepts and responds to one or more incoming network packets associated with the host off-loadable packet exchange sequence while the host processor is in a sleep mode state or is transitioning between sleep mode states.

Abstract: A communication device includes a DC input component, a transmitting component an envelope detecting component, a receiving component, a storage component and a comparator. The DC input component generates a first direct current signal and a second direct current signal. The transmitting component generates a first transmitted signal based on the first direct current signal and a second transmitted signal based on the second direct current signal. The envelope detecting component generates a first envelope signal based on the first transmitted signal and generates a second envelope signal based on the second transmitted signal. The receiving component generates a first received signal based on the first envelope signal and a second received signal based on the second envelope signal. The storage component has a priori information stored therein. The comparator outputs a correlation signal based on the first received signal, the second received signal and the a priori information.

Abstract: An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.