Abstract: Several methods and systems for encoding pictures associated with video data are disclosed. In an embodiment, a method includes determining by a processing module, whether a picture is to be encoded based on at least one of a skip assessment associated with the picture and an encoding status of a pre-selected number of pictures preceding the picture in an encoding sequence. The method further includes encoding by the processing module, a plurality of rows of video data associated with the picture upon determining that the picture is to be encoded, wherein the plurality of rows are encoded based on a pre-selected maximum encoded picture size.

Abstract: A memory circuit includes at least one bit cell that receives a word line, complementary bit lines and an array supply voltage and a word line suppression circuit. The word line suppression circuit includes two PFETs with their drains connected to the word line and their sources connected to the array supply voltage and an NFET with its source connected to ground and its drain connected to the word line. The NFET is inactivated before the PFETs are activated. One of the PFETs is activated before the other PFET is activated so as to control the slew rate of the word line and improve the static noise margin of the at least one bit cell.

Abstract: A resistive touch screen controller provides two-finger gesture recognition. Current mirror circuitry, coupled to the XP/XN and YP/YN conductors, generates a screen current IL corresponding to X/y plate currents, and a corresponding mirror current IL/N. A variable resistor receives mirror current IL/N, and a resistance controller sets the resistance value R1 of the variable resistor, and monitors a variable resistor voltage VR1 based on IL/N*R1. A processor determines calibration voltages for the X and Y plates corresponding to the mirror current IL/N for X/Y voltage values of VR1 for a no touch condition, and X/Y offset voltages VOFS and HOFS of VR1 for a two touch condition. For a two touch condition, the processor determines touch resistance relative to no touch, and generates an adjusted X/Y plate resistance ?X/?Y based on VOFS/HOFS, and based on X/Y, determines a distance and angle between the two touches.

Abstract: Described examples include multistage amplifier circuits having first and second forward circuits, a comparator or sensor circuit coupled to sense a signal in the second forward circuit to identify nonlinear operation or slewing conditions in the multistage amplifier circuit, and one or more sample hold circuits operative according to a sensor circuit output signal to selectively maintain the amplitude of an amplifier input signal in the second forward circuit and/or in a feedback circuit in response to the sensor circuit output signal indicating nonlinear operation or slewing conditions in the multistage amplifier circuit. Certain examples further include a clamping circuit operative to selectively maintain a voltage at a terminal of a Miller compensation capacitance responsive to the comparator output signal indicating nonlinear operation or slewing conditions.

Abstract: DC to DC converters and PWM controllers are presented in which a slope compensation ramp signal is provided for current control operation via a frequency adaptive compensation circuit with a phase locked loop that provides a control output signal having an amplitude generally proportional to the frequency of a clock signal, and a slope generator circuit generating the slope compensation ramp signal with an amplitude generally proportional to the control output signal amplitude.

Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.

Abstract: A system can comprise a memory to store computer readable instructions and a processing unit to access the memory and to execute the computer readable instructions. The computer readable instructions can comprise a certificate manager configured to request generation of N number of random values, where N is an integer greater than or equal to one. The certificate manager can also be configured to request a digital certificate from at least one certificate authority of at least two different certificate authorities. The request can include a given one of the N number of random values. The certificate manager can also be configured to generate a private key of a public-private key pair, wherein the private key is generated based on a private key of each of the least two certificate authorities.

Abstract: This invention measures the propagation delay ?1 between the user equipment and a first cooperating unit and the propagation delay ?2 between the user equipment and a second cooperating unit. These propagation delays are used to compute a timing advance amount to the user equipment to enable coordinated multi-point reception. In a first embodiment one cooperating unit receives a function of the propagation delay, computes the timing advance amount and transmits a timing advance command to the user equipment. In a second embodiment a central unit performs these operations.

Abstract: A method of fabricating a semiconductor device includes forming at least one trench from a top side of a semiconductor layer, wherein the trench is lined with a trench dielectric liner and filled by a first polysilicon layer. The surface of the trench dielectric liner is etched, wherein dips in the trench dielectric liner are formed relative to a top surface of the first polysilicon layer which results in forming a protrusion including the first polysilicon layer. The first polysilicon layer is etched to remove at least a portion of the protrusion. A second dielectric layer is formed over at least the trench after etching the first polysilicon layer. A second polysilicon layer is deposited. The second polysilicon layer is etched to remove it over the trench and provide a patterned second polysilicon layer on the top side of the semiconductor layer.

Abstract: An electrostatic discharge (ESD) protection circuit (FIG. 3C) is disclosed. The circuit includes a bipolar transistor (304) having a base, collector, and emitter. Each of a plurality of diodes (308-316) has a first terminal coupled to the base and a second terminal coupled to the collector. The collector is connected to a first terminal (V+). The emitter is connected to a first power supply terminal (V?).

Abstract: This invention is a System On a Chip (SOC) requiring two tamper resistant externally generated power supplies. A first, higher power supply powers I/O and analog circuits. A second, lower power supply powers digital circuits and memory. A first voltage monitor circuit powered by said first power supply generates a first output signal when the first power supply is below an operational limit high level. A second voltage monitor circuit powered by said first power supply indicates when the second power supply is above an operational high limit level. A power switch is controlled by the first voltage monitor circuit. This power switch connects the second power supply and second load when closed and isolates them when open. Thus the memory cannot be accessed when the I/O and analog power supply is out of specification.

Abstract: Improved magnetic sensor excitation circuitry is presented for providing a periodic bidirectional excitation waveform to a fluxgate magnetic sensor excitation coil using a bridge circuit connected to the excitation coil and having lower transistors for switched selective connection to a current mirror input transistor to mirror a current provided by pulsed current source, and with integrated filtering to control pulse rise times and slew rate.

Abstract: A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110) with a MEMS mechanical element (111) of a first height (111a) assembled on the pad and connected to the terminals by wires (120) with an insulating coat (121); a ridge (130) on the substrate, which surrounds the MEMS element (111) with a second height (130c) greater than the first height and comprises a plastic compound (131) filled with particles (132) and a surface (130a, 130b) having an adhering moisture-impermeable seal layer (133); and a moisture-impervious lid (140) attached to the ridge by moisture-proof bonds (150, 151), sealing the volume (160) enclosed by the lid, the chip, and the metalized ridge as a hermetic space for the MEMS element (111).

Abstract: The invention relates to an apparatus and method for tracking energy consumption. An energy tracking system comprises at least one switching element, at least one inductor and a control block to keep the output voltage at a pre-selected level. The switching elements are configured to apply the source of energy to the inductors. The control block compares the output voltage of the energy tracking system to a reference value and controls the switching of the switched elements in order to transfer energy for the primary voltage into a secondary voltage at the output of the energy tracking system. The electronic device further comprises an ON-time and OFF-time generator and an accumulator wherein the control block is coupled to receive a signal from the ON-time and OFF-time generator and generates switching signals for the at least one switching element in the form of ON-time pulses with a constant width ON-time.

Abstract: A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the positions of a first subgroup of micromirrors of a reset group are set based on a first portion of a first bitplane and the positions of a second subgroup of micromirrors of the same reset group are set based on a first portion of a second bitplane. Then, in a second reset operation, the positions of the first subgroup are set based on a second portion of the second bitplane and the positions of the second subgroup are set based on a second portion of a first bitplane. In one example, subsets of alternating rows of micromirrors of the same reset group are successively set according to alternating data corresponding to different ones of first and second bitplanes.

Abstract: A radio that includes a transceiver to transmit and receive RF signals. The transceiver including a transmitter, a transformer, and a receiver, the transformer is coupled to and shared between the transmitter and the receiver. A resonator is formed by the combination of the transformer and capacitive elements of the transmitter and receiver.

Abstract: Systems and methods for setting a Network Allocation Vector (NAV) in a PLC node are disclosed. In a PLC standard, coexistence is achieved by having the nodes detect a common preamble and backing off by a Coexistence InterFrame Space (cEIFS) time period to help the node to avoid interfering with the other technologies. In one embodiment, a PHY primitive is sent from the PHY to the MAC know that there has been a preamble detection. A two-level indication may be used—one indication after receiving the preamble and other indication after decoding the entire frame. The MAC sets NAV to EIFS if a native preamble is detected. The MAC sets NAV to cEIFS if only a coexistence preamble is detected or if a non-native preamble is detected.

Abstract: A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can include a shield residing on a given side of a substrate spaced apart from the transmitting coil. The shield can be configured to filter an electric field induced by the transmitting coil.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Abstract: Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.