Abstract: An integrated circuit (IC) die has a top side surface providing circuitry including active circuitry configured to provide a function, including at least one bond pad formed from a bond pad metal coupled to a node in the circuitry. A dielectric passivation layer is over a top side surface of a substrate providing a contact area which exposes the bond pad. A metal capping layer includes an electrically conductive metal or an electrically conductive metal compound over at least the contact area to provide corrosion protection to the bond pad metal, which is in electrical contact with the bond pad metal. The metal capping layer can extend over structures other than the bond pads, such as to cover at least 80% of the area of the IC die to provide structures on the IC die protection from incident radiation.

Abstract: Deblocking filtering is provided in which an 8×8 filtering block covering eight sample vertical and horizontal boundary segments is divided into filtering sub-blocks that can be independently processed. To process the vertical boundary segment, the filtering block is divided into top and bottom 8×4 filtering sub-blocks, each covering a respective top and bottom half of the vertical boundary segment. To process the horizontal boundary segment, the filtering block is divided into left and right 4×8 filtering sub-blocks, each covering a respective left and right half of the horizontal boundary segment. The computation of the deviation d for a boundary segment in a filtering sub-block is performed using only samples from rows or columns in the filtering sub-block. Consequently, the filter on/off decisions and the weak/strong filtering decisions of the deblocking filtering are performed using samples contained within individual filtering blocks, thus allowing full parallel processing of the filtering blocks.

Abstract: Embodiments of methods and systems for adaptive sub-band point-to-point communication are presented. In one embodiment a method includes performing functions using a power line communication (PLC) transmitter device. The method may include generating a first data packet having a first adaptive sub-band information set, the first sub-band information set comprising information to be used by a PLC receiver for determining a sub-band hopping pattern. The method may also include transmitting the first data packet on a first PLC sub-band. Additionally, the method may include hopping to a second PLC sub-band, and generating a second data packet having a second adaptive sub-band information set, the second sub-band information set comprising information to be used by the PLC receiver for determine the sub-band hopping pattern. The method may further include transmitting the second data packet on the second PLC sub-band.

Abstract: An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A method of separating dice of a singulated wafer that is supported on a dicing tape sheet is disclosed. The method may include attaching the dicing tape sheet to a ring frame; relatively raising a portion of the dicing tape sheet supporting the wafer with respect to the ring frame; and attaching support tape to the ring frame and the dicing tape sheet.

Abstract: Methods and apparatus for frequency offset estimation and correction prior to preamble detection of DSSS signals. An integrated circuit is disclosed including a receiver circuit having an input coupled to receive a DSSS signal, the receiver circuit configured to sample the DSSS signal and to output a sequence of digital samples; carrier frequency offset estimation logic configured to perform a carrier frequency offset estimation on the digital samples; carrier frequency correction logic configured to correct the carrier frequency of the sequence of digital samples using the carrier frequency offset estimation and to output a sequence of corrected digital samples; offset quadrature phase shift keying (O-QPSK) demodulation logic configured to perform demodulation on the corrected digital samples and further configured to output symbols corresponding to the corrected digital samples; and preamble identification configured to identify and detect a preamble sequence in the symbols.

Abstract: A networking device includes a packet header protect generator, a transmitter, a receiver, a decoder and router. The transmitter transmits a data packet to the receiver. The data packet includes a data packet header. The packet header protection generator is arranged to toggle selected bits of a protected portion of the data packet header and generate a data integrity signature. The receiver receives the data packet and generates a received data integrity signature. The decoder computes a locally computed data integrity signature in response to the protected portion of the received data packet header. The locally computed data integrity signature is compared with the received data integrity signature. The router selects a portion of a routing path in response to whether a data packet forwarding destination includes a decoder arranged to compute a locally computed data integrity signature.

Abstract: An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm?3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.

Abstract: A power gated electronic device that includes a power supply domain coupled to a power gate switch, a comparator, and control logic. The power supply domain is configured to receive voltage from a power supply. The comparator is configured to receive voltage from the power supply domain and compare the voltage from the power supply domain with a threshold level. The control logic is configured to receive the output of the comparator and, based on the comparison between the voltage from the power supply domain and the threshold level, cause the power supply domain to pulldown.

Abstract: A microelectronic device containing a piezoelectric thin film element is formed by oxidizing a top surface of a piezoelectric layer with an oxygen plasma, and subsequently forming an etch mask containing photoresist on the oxidized top surface. The etch mask is conditioned with an oven bake followed by a UV bake. The piezoelectric layer is etched using a three step process: a first step includes a wet etch of an aqueous solution of about 5% NH4F, about 1.2% HF, and about 18% HCl, maintaining a ratio of the HCl to the HF of about 15.0, which removes a majority of the piezoelectric layer. A second step includes an agitated rinse. A third step includes a short etch in the aqueous solution of NH4F, HF, and HCl.

Abstract: An electronic device that includes a power on reset, a variable power supply filter coupled to the power on reset, and control logic coupled to the power on reset and the variable power supply filter. The control logic is configured to activate the variable power supply filter based on a core domain of the electronic device being active.

Abstract: A microelectronic device containing a piezoelectric component is formed sputtering an adhesion layer of titanium on a substrate by an ionized metal plasma (IMP) process. The adhesion layer is oxidized so that at least a portion of the titanium is converted to a layer of substantially stoichiometric titanium dioxide (TiO2) at a top surface of the adhesion layer. A layer of platinum is formed on the titanium dioxide of the adhesion layer; the layer of platinum has a (111) crystal orientation and an X-ray rocking curve FWHM value of less than 3 degrees. A layer of piezoelectric material is formed on the layer of platinum. The piezoelectric material may include lead zirconium titanate.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: Assessing open circuit and short circuit defect levels in circuits implemented in state of the art ICs is difficult when using conventional test circuits, which are designed to assess continuity and isolation performance of simple structures based on individual design rules. Including circuit blocks from ICs in test circuits provides a more accurate assessment of defect levels expected in ICs using the circuit blocks. Open circuit defect levels may be assessed using continuity chains formed by serially linking continuity paths in the circuit blocks. Short circuit defect levels may be assessed by using parallel isolation test structures formed by linking isolated conductive elements in parallel to buses. Forming isolation connections on a high metal level enables location of shorted elements using voltage contrast on partially deprocessed or partially fabricated test circuits.

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Abstract: A device test architecture and a reduced device test interface are provided to enable efficient testing of embedded cores and other circuits within devices. The reduced device test interface is achieved using a double data rate (DDR) signaling technique between the tester and the device. The DDR test interface allows the tester to interface to test circuits within the device, such as IEEE 1500 and/or IEEE 1149.1 test circuits, to provide high test data bandwidth to the test circuits using a minimum of test interface signals. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester.

Abstract: A single supply level shifter converts an input logic level IN into level shifted OUT and OUT_X. An IN inverter generates level-shifted OUT at an OUT Node. IN is coupled at an INT Node to a VDD supply rail, through an INT_Node PFET that controls the INT Node based on OUT_X. An OUT_X network includes a separate IN_X inverter (generating inverted IN independent of level shifting), and an OUT_X circuit that controls pull-up/down of an OUT_X Node to generate level-shifted OUT_X, receiving control inputs from both IN and IN_X inverters. The OUT_X circuit is a three FET stack: a pull-up/down PFET/NFET pair receives IN_X, and an OUT_X Node control PFET, coupled between the pull-up PFET and the OUT_X Node, receives OUT. Based on OUT and IN_X, the OUT_X circuit generates OUT_X as an inverted OUT (including supplying OUT_X to the INT_Node PFET to control the INT Node (including OUT pull-up).

Abstract: An electronic tracing process includes packing both stall (215) and reason (219) data into a single high priority timing information stream. An integrated circuit includes an electronic processor (110), and a tracing circuit (120) operable to pack both stall and events data into a single timing information stream. Other circuits, processes and systems are also disclosed.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.