Patents Assigned to Texas Instruments
  • Publication number: 20090090990
    Abstract: Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Applicant: Texas Instruments, Incorporated
    Inventors: Hiroaki Niimi, Manoj Mehrotra
  • Patent number: 7515548
    Abstract: Determining the reasons for packet loss in a wireless local area network; such as an IEEE 802.11 network. The method uses the strength of received signals at a wireless station, such as the received signal strength indicator (RSSI), noise levels (e.g, non-802.11 energy in the 2.4 GHz frequency range), and packet loss information together to determine the network status. In most implementations, the 802.11 implementation (e.g., the 802.11 driver) is responsible for maintaining statistics on the RSSI and the noise whereas the measure of the packet loss is the responsibility of the application. The network status is determined by the endpoint station independent from the access point.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Praphul Chandra, David Lide, Manoj Sindhwani
  • Patent number: 7514304
    Abstract: A MOSFET device (100) in a mono-crystalline semiconductor material (101) of a first conductivity type, which comprises a source and a drain of the opposite conductivity type, each having regions of polycrystalline semiconductor (110, 120) and respective junctions (112a, 122a) in monocrystalline semiconductor. Localized buried insulator regions (113, 123) are below the polycrystalline source and drain regions, and a gate (130) between the source and drain regions is located so that the gate channel (134) is formed in bulk mono-crystalline semiconductor material. As an example, the semiconductor is silicon, the first conductivity type is p-type, and the localized buried insulator is silicon dioxide. The semiconductor material may also include silicon germanium.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory E. Howard
  • Patent number: 7514292
    Abstract: An integrated circuit (IC) chip, mounted on a leadframe, has a network of power distribution lines deposited on the surface of the chip so that these lines are located over active components of the IC, connected vertically by metal-filled vias to selected active components below the lines, and also by conductors to segments of the leadframe. Furthermore, the lines are fabricated with a sheet resistance of less than 1.5 m?/· and the majority of the lines is patterned as straight lines between the vias and the conductors, respectively.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Taylor R Efland, Milton L Buschbom, Sameer Pendharkar
  • Patent number: 7515392
    Abstract: Transistors of low voltage specification are used to process information in a signal received at a high(er) voltage level. A protection circuit ensures that the cross terminal voltages do not exceed an allowed maximum voltage (e.g., 2.4 V for transistors of 1.8V specification). In an embodiment, the protection circuit contains a PMOS transistor which turns off if a protected cross terminal voltage exceeds such allowed maximum voltage. As a result, protection may be provided while consuming minimal power. The protection circuit may be employed in various types of circuits such as input buffers and logic gates. The protection circuits and the input buffers may potentially be implemented using transistors of a single voltage specification.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Sanish Koshi Jacob
  • Patent number: 7515746
    Abstract: A method of color-matching the images generated by multiple projectors (11) of a tiled projection systems. Each projector (11) has its own processing unit (34), and stores color and luminance data associated with that projector (11). A main controller (13) in data communication with each projector (11) receives the color and luminance data and, for each projector, calculates color correction data for that projector. The main controller (13) delivers the correction data to each processor (11), which then uses the correction data to adjust the values of its pixel data.
    Type: Grant
    Filed: August 31, 2001
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Gregory S. Pettitt
  • Patent number: 7515161
    Abstract: A system and method for reducing pulse width modulation contouring artifacts. Each input intensity value is translated to at least one non-binary bit pattern for display. Many of the input intensity values are translated to at least two alternate non-binary bit patterns. The alternate codes are used to smooth the transition between intensity codes as major bits are turned on. The smoothing occurs by the gradual transition from codes that do not use the major bit to codes that do use the major bit. Typically the alternate codes are selected based on the location of the pixel in a spatial pattern (100) and the alternate codes are spatially alternated from one pixel (102) to the next (104). Other embodiments temporally alternate the codes from one period—typically a frame period—to the next. Still other embodiments alternate the codes both spatially and temporally.
    Type: Grant
    Filed: May 17, 2000
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Daniel J. Morgan
  • Patent number: 7514012
    Abstract: The present invention discloses a method for processing a deformable element of a microstructure for reducing the plastic deformation by oxidizing the deformable element. The method of the present invention can be performed at a variety of stages of the fabrication and packaging processes.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan Doan, Satyadev R. Patel, Dmitri Simonian
  • Patent number: 7514331
    Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Jong Shik Yoon, Amitava Chatterjee, Haowen Bu
  • Patent number: 7514329
    Abstract: Extended-drain MOS transistor devices and fabrication methods are provided, in which a drift region of a first conductivity type is formed between a drain of the first conductivity type and a channel. The drift region comprises first and second portions, the first portion extending partially under a gate structure between the channel and the second portion, and the second portion extending laterally between the first portion and the drain, wherein the first portion of the drift region has a concentration of first type dopants higher than the second portion.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sameer Pendharkar, Ramanathan Ramani, Taylor R. Efland
  • Patent number: 7515324
    Abstract: A system for, and method of resolving reset conflicts in a phased-reset SLM system and a projection visual display system incorporating the system or the method. In one embodiment, the system includes a reset conflict arbiter configured to receive reset instructions containing conflicts from a sequence generator and resolve the conflicts by shifting an execution time of a selected one of the reset instructions according to a conflict resolution method.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Sue Hui
  • Patent number: 7516378
    Abstract: Scan distributor, collector, and controller circuitry connect to the functional inputs and outputs of core circuitry on integrated circuits to provide testing through those functional inputs and outputs. Multiplexer and demultiplexer circuits select between the scan circuitry and the functional inputs and outputs. The core circuitry can also be provided with built-in scan distributor, collector, and controller circuitry to avoid having to add it external of the core circuitry. With appropriately placed built-in scan distributor and collector circuits, connecting together the functional inputs and outputs of the core circuitry also connects together the scan distributor and collector circuitry in each core. This can provide a hierarchy of scan circuitry and reduce the need for separate test interconnects and multiplexers.
    Type: Grant
    Filed: August 10, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7515077
    Abstract: In an analog-to-digital converter used to convert and store in buffer registers signals from a plurality of peripheral devices, a mode is provided wherein, for selected peripherals, the most recent converted signal overlays the previously stored signal in the buffer registers.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Sunil S. Oak
  • Patent number: 7514734
    Abstract: Hardmasks and fabrication methods are presented for producing ferroelectric capacitors in a semiconductor device, wherein a hardmask comprising aluminum oxide or strontium tantalum oxide is formed above an upper capacitor electrode material, and capacitor electrode and ferroelectric layers are etched to define a ferroelectric capacitor stack.
    Type: Grant
    Filed: September 6, 2005
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sanjeev Aggarwal, Kelly J. Taylor, Theodore S. Moise
  • Patent number: 7514309
    Abstract: A semiconductor device is fabricated with a protective liner and/or layer. Well regions and isolation regions are formed within a semiconductor body. A gate dielectric layer is formed over the semiconductor body. A gate electrode layer, such as polysilicon, is formed on the gate dielectric layer. A protective gate liner is formed on the gate electrode layer. A resist mask is formed that defines gate structures. The gate electrode layer is patterned to form the gate structures. Offset spacers are formed on lateral edges of the gate structures and extension regions are then formed in the well regions. Sidewall spacers are then formed on the lateral edges of the gate structures. An NMOS protective region layer is formed that covers the NMOS region of the device. A recess etch is performed within the PMOS region followed by formation of strain inducing recess structures.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Seetharaman Sridhar, Craig Hall, Che-Jen Hu, Antonio Luis Pacheco Rotondaro
  • Patent number: 7516037
    Abstract: A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: David John Baldwin, Eric Blackall, Joseph Devore, Ross E. Teggatz
  • Patent number: 7514308
    Abstract: The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (100), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device (120) having a first gate dielectric layer (133) and a first gate electrode layer (138) located over a substrate (110), wherein the first gate dielectric layer (133) has an amount of nitrogen located therein. In addition to the PMOS device (120), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device (160) having a second gate dielectric layer (173) and a second gate electrode layer (178) located over the substrate (110), wherein the second gate dielectric layer (173) has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device (120) and the NMOS device (160).
    Type: Grant
    Filed: May 8, 2007
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Ajith Varghese, Husam N. Alshareef, Rajesh Khamankar
  • Patent number: 7516069
    Abstract: A method for performing time and frequency Signal-to-Noise Ratio (SNR) dependent weighting in speech recognition is described that includes for each period t estimating the SNR to get time and frequency SNR information ?t,f; calculating the time and frequency weighting to get ?tf; performing the back and forth weighted time varying DCT transformation matrix computation MGtM?1 to get Tt; providing the transformation matrix Tt and the original MFCC feature ot that contains the information about the SNR to a recognizer including the Viterbi decoding; and performing weighted Viterbi recognition bj(ot).
    Type: Grant
    Filed: April 13, 2004
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Alexis P. Bernard, Yifan Gong
  • Publication number: 20090089570
    Abstract: A method, system and apparatus for executing a boot loader for an embedded system including a system-on-chip (SOC) processor coupled to a memory including first boot loader code for implementing a first boot loader stored in a first sector and second boot loader code for implementing a second boot loader stored in a second sector determines which of the first boot loader code and second boot loader code is younger; if the second boot loader code is determined to be younger than the first boot loader code, a swapping operation is performed so that the second boot loader code is associated with the first sector and the first boot loader code is associated with a different sector, and the boot loader code associated with the first sector is executed.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Applicant: Texas Instruments Incorporated
    Inventor: Vitaly Andrianov
  • Patent number: 7511648
    Abstract: A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (?Vbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (?Vbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue?Vref or 2×Vresidue+Vref.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: March 31, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Dimitar T. Trifonov, Jerry L. Doorenbos