Abstract: An algorithm for the promotion of terminal nodes to switch nodes in a PLC network reduces overall network overhead and collisions, while ensuring the appropriate selection of a switch node and minimizing the number of levels in a PLC network. It also ensures that the terminal nodes with appropriate signal-to-noise ratios (SNRs) are promoted. It is desirable to have a network with fewer levels. The disclosed approach favors the nodes that are closer to the DC to promote them as switch nodes. This is achieved by waiting for a smaller number of PNPDUs for a node that is closer to the DC in comparison to a node that is farther away from the DC.

Abstract: A replacement metal gate transistor is formed with high quality gate dielectric under the high-k dielectric. The high quality gate dielectric is formed on the substrate at a temperature of at least 850° C. A sacrificial gate dielectric is formed on the high quality gate dielectric and a polysilicon replacement gate is formed on the sacrificial gate dielectric. The polysilicon replacement gate is removed leaving a gate trench. The sacrificial gate dielectric is removed from a bottom of the gate. A high-k dielectric is deposited into the gate trench. Metal gate material is deposited on the high-k dielectric.

Abstract: A level shifter is provided. This level shifter includes a first driver, a second driver, a capacitor, and a common mode circuit. The first driver has a first signal path that is coupled between an input terminal and an output terminal, and the first driver operates in a first voltage domain. The second operates in a second voltage domain and includes a second signal path and latch. The second signal path is coupled between an input terminal and an output terminal of the second driver, and the latch that is coupled to the input terminal of the second signal path. The capacitor that is coupled between the output terminal of the first signal path and the input terminal of the second signal path, and the bias circuit is coupled to the input terminal of the second signal path and operates in the second voltage domain.

Abstract: A motor controller includes a square wave voltage generator and adding circuitry for adding the square wave voltage to a first drive voltage that is connectable to the stator windings of a motor. A current monitor for monitoring the input current to the motor as a result of the square wave voltage. A device for determining the position of the rotor based on the input current.

Abstract: This invention assures cache coherence in a multi-level cache system upon eviction of a higher level cache line. A victim buffer stored data on evicted lines. On a DMA access that may be cached in the higher level cache the lower level cache sends a snoop write. The address of this snoop write is compared with the victim buffer. On a hit in the victim buffer the write completes in the victim buffer. When the victim data passes to the next cache level it is written into a second victim buffer to be retired when the data is committed to cache. DMA write addresses are compared to addresses in this second victim buffer. On a match the write takes place in the second victim buffer. On a failure to match the controller sends a snoop write.

Abstract: This invention is codebook sub-sampling of the reporting of RI, CQI, W1 and W2. If CSI mode 1 is selected RI and W1 are jointly encoded using codebook sub-sampling in report 1. If CSI mode 2 is selected W1 and W2 are jointly encoded using codebook sub-sampling in report 2.

Abstract: An ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device. A method of forming an ESD protection circuit with a diode string coupled to a diode-isolated, gate-grounded NMOS ESD device.

Abstract: A voltage feedback loop employed with a power distribution switch rapidly responds to a predetermined drop in output voltage to increase the resistance of the switch for a predetermined time. After this predetermined time, a current feedback loop controls the resistance until the output voltage recovers, while also isolating the voltage feedback loop from the switch.

Abstract: A DC-DC converter has a high-side transistor series with a low-side transistor and an inductor connected to a node therebetween, a gate driver circuit has a high-side gate driver circuit coupled to the high-side transistor; a low-side gate driver circuit coupled to the low-side transistor; a minimum pulse with circuit coupled to one of the high-side and low-side gate, the minimum pulse width circuit adaptively controlling a pulse width of a drive signal to the high-side or low-side transistor by the propagation delay of the respective gate driver circuit.

Abstract: A method of transmitting a wireless signal (FIGS. 3A-3C) is disclosed. A data stream is divided (306) into a first data stream and a second data stream. The first data stream is encoded (300) at a first data rate. The second data stream is encoded (320) at a second data rate different from the first data rate. A first part of the encoded first data stream is transmitted from a first transmit antenna (308). A second part of the encoded first data stream is transmitted from a second transmit antenna (312).

Abstract: An integrated circuit contains a high precision capacitor having a bottom plate, a dielectric layer over the bottom plate, a capacitor opening in the dielectric layer exposing, and not overlapping, the bottom plate, a capacitor dielectric layer covering sidewalls and a bottom of the capacitor opening, a top plate covering the capacitor dielectric layer in the capacitor opening, and a capacitor planarizing dielectric layer covering the capacitor top plate in the capacitor opening. A top surface of the capacitor planarizing dielectric layer and a top edge of the capacitor top plate are substantially coplanar. The top plate does not extend laterally beyond the capacitor opening. A method of forming the integrated circuit the high precision capacitor is also disclosed.

Abstract: An integrated circuit (IC) for driving a light emitting semiconductor device is provided. The IC includes an input stage configured to receive a first input signal with a first differential pair of bipolar transistors and a second input signal with a second differential pair of bipolar transistors and to provide a pre-driver output signal being a superposition of the first input signal and the second input signal and an output stage including a third differential pair of bipolar transistors for receiving the pre-driver output signal of the input stage and for driving the light emitting semiconductor device in response to the pre-driver output signal, wherein the IC is configured to pre-distort the pre-driver output signal of the input stage so as to compensate a signal distortion of the output stage.

Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

Abstract: Elements of a single beam-forming array of ultrasonic transducer elements are selectively activated to direct two or more ultrasonic beams to a series of acoustic mirrors mounted to or fabricated at known locations at an inside surface of the pipe. The ultrasonic beams traverse measurement path segments at known angles through a fluid flowing through the pipe before being received back at the single transducer array. Fluid flow velocity along the fluid flow path is calculated as a function of a difference in time-of-flight (TOF) along first and second ultrasonic beam paths after subtracting TOF components contributed by known-length non-measurement path segments. The difference in TOF results from an additive downstream fluid flow velocity vector component along a first measurement path segment and a subtractive upstream fluid flow velocity vector component along a second measurement path segment.

Abstract: A device includes a SAR, a comparator, a DAC and a multichannel passive S/H component. The multichannel passive S/H component is able to sample and hold a plurality of analog voltages in parallel. The multichannel passive S/H component is further able to serially feed the plurality of sampled and held analog voltages to the SAR, comparator and DAC, such that each analog voltage is serially converted to a digital representation.

Abstract: An adaptive transcoder is provided that includes a shared memory containing a plurality of decoder buffers to store incoming data packets, a plurality of decoder instances to control a decoding process to generate image raw data based on the incoming data packets, and a plurality of encoder instances configured to control an encoding process to generate outgoing packets based on the image raw data; and a data processing element containing a plurality of processing cores, and a core controller. Each decoder instance is paired with an encoder instance; and each decoder buffer is associated with a decoder instance. Each decoder buffer includes a monitoring element to monitor a respective decoder buffer, and provide buffer data corresponding to the status of the decoder buffer. Each encoder instance is associated with a processing core; and the core controller uses the buffer data to associate each decoder instance with a processing core.

Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

Abstract: A method (and related apparatus) includes receiving user input and generating at least one of schematic content for a circuit based on the received user input and a printed circuit board (PCB) layout based on the circuit. The method further includes generating a bill of material (BOM) for the circuit, and receiving a user selection of at least one of a computer-aided design (CAD) tool format and a PCB layout tool format. The method also includes receiving a user selection to include footprints for the components used in the schematic content or PCB layout and exporting at least one of the schematic content, and PCB layout as well as the PCB footprints to one or more files in accordance with the selected CAD and/or PCB layout tool format.

Abstract: An electronic device that includes a central processor and a coprocessor coupled to the central processor. The central processor includes a plurality of registers and is configured to decode a first set of instructions. The first set of instructions includes a command instruction and an identity of a destination register. The coprocessor is configured to receive the command instruction from the central processor, execute the command instruction, and write a result of the command instruction in the destination register. The central processor is further configured to set a register tag for the destination register at the time the central processor decodes the first set of instructions and to clear the register tag at the time the result is written in the destination register.

Abstract: This disclosure describes a test architecture that supports a common approach to testing individual die and dies in a 3D stack arrangement. The test architecture uses an improved TAP design to facilitate the testing of parallel test circuits within the die.