Abstract: Multi-threshold CMOS (MTCMOS) sequential circuits are presented with a first latch circuit formed of transistors with threshold voltages in a first range, along with a second latch circuit with inverters and a transfer gate formed of higher threshold voltage transistors for low-power retention of data from the first latch with power switching circuitry to selectively decouple inverters of the second latch circuit from a voltage supply during low-power retention mode operation of the sequential circuit.

Abstract: In example embodiments disclosed herein, a primary wireless device infrequently sends a ping to a secondary device to determine if there are any communications from an access point intended for the primary wireless device. The secondary device, ideally connected to wall power, is wirelessly connected to the access point, acting as a connected proxy so that the primary wireless device, typically battery powered, does not always have to be connected. In a situation in which an incoming communication is intended for the primary device, the secondary device receives the notification and buffers whatever is sent from the access point intended for the primary wireless device and acknowledges the receipt. Then, when the primary wireless device pings the secondary device, the secondary device sends the buffered communication to the primary wireless device. As far as the access point is concerned, it thinks it is communicating directly with primary wireless device.

Abstract: Systems and methods for enhanced carrier sense multiple access (CSMA) protocols are described. In various implementations, these systems and methods may be applicable to Power Line Communications (PLC). For example, a method may include attempting to access a communications channel to transmit a frame after a backoff time proportional to a randomly generated number within a contention window (CW), the CW having an initial value carried over from a previous transmission of a different frame. Additionally or alternatively, some of techniques described herein may facilitate the spreading of the time over which devices attempt to transmit packets, thereby reducing the probability of collisions using, for example, Additive Decrease Multiplicative Increase (ADMI) mechanisms.

Abstract: A method and apparatus for image coding using hierarchical sample adaptive band offset. The method includes decoding a signal of a portion of an image, determining a band offset type and offset of a portion of the image, utilizing the band offset type and offset to determine a sub-band, and reconstructing a pixel value according to the determined offset value.

Abstract: A method of making an integrated circuit (IC) package including electrically and physically attaching a die to an interposer, attaching the interposer to a bottom leadframe, attaching a discrete circuit component to the interposer and attaching a top leadframe to the bottom leadframe.

Abstract: Integrated circuits and methods for deactivating user circuit operation with one or more wide channel sensing transistors biased to an on condition for exposure to total ionizing dose and then to an off condition for measurement and comparison of a leakage current or threshold voltage parameter to a predetermined reference, and a deactivation circuit selectively disables operation of the user circuit if the sensed parameter is greater than or equal to the reference.

Abstract: One or more high-order bit linear branches of a segmented DAC are implemented as R-2R networks geometrically down-scaled from the DAC binary portion by a selected factor. The resulting increase in closely-located mismatch is compensated for by implementing a trim circuit at a low-order end of each such linear branch. The trim circuit is designed with a number of trim steps to compensate for the selected linear branch down-scaling factor. Each trim step switches a resistance into the low-order end of the linear branch resulting in an even resistance increment or decrement at the lumped linear branch output. The trim circuit is calibrated to provide an amount of trim at the linear branch output such that the lumped resistance of the trimmed linear branch matches the lumped resistance of the binary portion within a selected tolerance (e.g., generally +/?0.5 LSB).

Abstract: A communication device includes a modulating component, a transmitting component and a controlling component. The modulating component generates a first modulated packet and a second modulated packet. The first modulated packet is based on a first modulation scheme and the second modulated packet is based on a second modulation scheme. The first modulation scheme has a first amount of energy associated therewith, and the second modulation scheme has a second amount of energy associated therewith. The first amount of energy is less than the second amount of energy. The transmitting component generates a transmit packet based on one of the first modulated packet and the second modulated packet. The controlling component generates a control signal to instruct the modulating component to generate the first modulated packet when the transmit packet will be less than a predetermined threshold. The threshold is based on the first amount of energy.

Abstract: Coupling circuits for power line communication (PLC) devices are described. In an embodiment, a PLC device may comprise a processor and a coupling circuit coupled to the processor. The coupling circuit may in turn comprise a transmitter path and a receiver path. In some implementations, the transmitter path may include a first amplifier, a first capacitor coupled to the first amplifier, a first transformer coupled to the first capacitor, and a plurality of line interface coupling circuits coupled to the first transformer, where each of the line interface coupling circuits is configured to be connected to a different phase of an electrical power circuit. Meanwhile, the receiver path may include a plurality of capacitors, where each of the plurality of capacitors coupled to a corresponding one of the line interface circuits, a filter network coupled to the plurality of capacitors, and a second amplifier coupled to the filter network.

Abstract: The disclosure provides an asynchronous FIFO circuit that includes a data memory which is coupled to a write data path and a read data path. The data memory receives a write clock and a read clock. A FIFO write pointer counter receives a write enable signal and the write clock. The FIFO write pointer counter provides a FIFO write pointer signal to the data memory. A FIFO read pointer counter receives a read enable signal and the read clock. The FIFO read pointer counter provides a FIFO read pointer signal to the data memory. A control circuit receives the write enable signal, the read enable signal, the FIFO write pointer signal, the FIFO read pointer signal, the write clock and the read clock. The control circuit generates a memory full signal when the data memory is full and a memory empty signal when the data memory is empty.

Abstract: A magnetically-coupled structure is integrated with an integrated circuit in back end-of-line (BEOL) digital CMOS fabrication processes. A differential primary (or secondary) coil is formed by patterning a thick copper (Cu) metal layer, and a single-ended secondary (or primary) coil is formed by patterning a thick aluminum (Al) top metal bonding layer. Crossovers and/or cross-unders are formed using thin metal layers. One embodiment provides a stacked balun with a differential primary input winding defined in the copper layer, directly underneath a single-ended spiral winding defined in the aluminum layer. The spiral forms the single-ended secondary output of the balun and is rotated by 90° to prevent metal shorting for its cross-under connections. Another embodiment provides a transformer with one differential primary (or secondary) coil defined in the copper layer and another differential secondary (or primary) coil defined in the aluminum layer and adding a center tap.

Abstract: A controller area network (CAN) node comprises an internal high differential bus line (CANH) and an internal low differential bus line (CANL). The CAN node further comprises a receiver (RXD) comparator coupled to both the internal CANH and the internal CANL that outputs an internal RXD signal. The CAN node further comprises an RXD dominant time out (DTO) circuit. The RXD DTO circuit includes: a) an RXD dominant transition detector coupled to an output of the RXD comparator; b) a timer triggered by the RXD dominant transition detector detecting a dominant RXD transition; c) an RXD dominant timer comparator that is coupled to an output of the timer which compares an output of the timer to a selected value; d) an internal RXD dominant signal is changed to an RXD DTO recessive signal after a selected time interval has lapsed and can include a fault output to signal this fault condition.

Abstract: An integrated circuit and method with a metal gate transistor and with a Schottky diode where the metal used to form the Schottky diode is the metal used to form the metal gate.

Abstract: A system is provided for calibrating a device. The system includes a reference component, a sampling component, a calibration component, a comparing component and a proportional integral component. The reference component provides a reference power signal based on a voltage instruction and a current instruction. The sampling component samples a voltage signal to obtain a sampled voltage value and samples a current signal to obtain a sampled current value. The calibration component generates a calibrated power signal based on the sampled voltage value and the sampled current. The comparing component generates an error signal based on the reference power signal and the calibrated power signal. The proportional integral component and the calibration component are a feedback system that is operable to calibrate the gain of the sampled voltage and the sample current based on the error signal.

Abstract: A switched mode assisted linear (SMAL) amplifier/regulator architecture can be configured to supply regulated power to a dynamic load, such as an RF power amplifier. Embodiments of a SMAL regulator can include a linear amplifier and a switched mode converter parallel coupled at a supply node, and configured such that the amplifier sets load voltage, while the amplifier and the switched converter are cooperatively controlled to supply load current. The amplifier can include separate feedback loops: an external relatively lower speed feedback loop for controlling signal path bandwidth, and an internal relatively higher speed feedback loop for controlling output impedance bandwidth of the linear amplifier. The linear amplifier can be AC coupled to the supply node, and the switched converter can be configured with a capacitive charge control loop that controls the switched converter to effectively control the amplifier to provide capacitive charge control.

Abstract: An integrated circuit with a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair. A method for forming a matching resistance heater. A method for operating an SOI integrated circuit containing a matched transistor pair with a matching resistance heater coupled to each transistor of the matched transistor pair.

Abstract: A dual edge triggered retention flip-flop reduces clock tree power dissipation in an active mode and leakage power in a low-power (e.g., standby) mode. For example, a first latch can be used to latch a first state of an input to a flip-flop in response to a first (e.g., positive-going) edge of a clock signal and a second latch can be used to latch a second state of the input to the flip-flop in response to a second (e.g., negative-going) edge of a clock signal. A retention latch can be used to latch and retain the state of the flip-flop when the first and second latches are disabled to save power in the low-power mode. The retention latch can also be used to initialize at least one of the first and second flip-flops when exiting the low-power mode.

Abstract: An apparatus and method for controlling a haptic actuator. A haptic actuator controller can includes driver input amplifier, an actuator feedback amplifier, an actuator driver, and a gain controller. The actuator driver is configured to drive a haptic actuator based on a difference of output of the input amplifier and output of the actuator feedback amplifier. The gain controller is configured to determine a boost interval for initiating motion of the haptic actuator, the boost interval based on a boost threshold back-electromotive-force (BEMF) voltage value exceeding a BEMF voltage generated by the haptic actuator. The gain controller is also configured to apply boost gains in the input amplifier and the feedback amplifier during the boost interval. The boost gains are higher than gains applied subsequent to the boost interval to maintain motion of the haptic actuator.

Abstract: A moveable dispenser assembly including is shown. The dispenser includes a reservoir having bonding adhesive therein including particles and a liquid carrier. The dispenser is moved to provide agitation to the dispenser for mixing the bonding adhesive into a homogeneous mixture of particles and the liquid carrier. An opening at an end of said dispenser dispenses the bonding adhesive onto a bonding location on the workpiece without removing the dispenser from the die attach apparatus. A one controller for sends a control signal that triggers moving of said moveable dispenser assembly for mixing said bonding adhesive before dispensing said volume of bonding adhesive onto said surface of said workpiece. The controller includes logic to control of movements such as oscillations to keep the bonding adhesive well mixed based on a comparing a parameter to be in a predetermined limit or range.

Abstract: A method for determining a photovoltaic (PV) current from each of a plurality of PV elements arranged in a differential network is provided. The differential network is controlled with a plurality of control signals, where the differential network includes a plurality of inductors, and each control signal has a duty cycle. A plurality of controller parameters is received from the plurality of differential controllers. The PV current for each of the plurality of PV elements is calculated from the plurality of inductor currents and the duty cycle for each control signal.