Patents Assigned to Texas Instruments
  • Patent number: 7518440
    Abstract: A dual path chopper-stabilized amplifier (100) includes first (11) and second (11A) chopping/notch-filtering paths, each including an input chopper (9,9A), a transconductance amplifier (2,2A), and a notch filter (15,15A). Chopping and notch filtering in the first path are controlled by first (CHOPCLK) and second (FILTERCLK) clock signals, respectively. Chopping and notch filtering in the second path are controlled by the second (FILTERCLK) and first (CHOPCLK) clock signals, respectively. Outputs of the first (15) and second (15A) switched capacitor notch filters are combined to provide an amplifier output signal (23A,B) that updates a capacitance (C4) at 4 times the frequency of the filter clock signal, to thereby improve amplifier stability without increasing clock frequency.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Dimitar T. Trifonov
  • Patent number: 7518386
    Abstract: The objective of the present invention is to provide a type of probe assembly with a long lifetime and low cost, as well as a type of probe card using same. Probe assembly 100 attached on the probe card has probe holder 200 that holds plural probes Q at prescribed positions and leaf spring mechanism 300 with probe holder 200 attached on it. Said leaf spring mechanism 300 has leaf spring cover 360 connected to probe card base plate 410 and leaf spring 330, as well as pin row base plate 310 with probe holder 200 attached on it. When the bump electrodes are contacted, pin row base plate 310 can move towards leaf spring cover 360 via leaf spring 330.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Takeshi Watanabe
  • Patent number: 7518053
    Abstract: Beat matching for two audio streams extracts beats from each, computes a conversion ratio from one stream to the other stream by an initial beat alignment plus a stability-maintaining beat alignment. A variable resampling converter or time scale modifier adjusts one stream to align beats with those of the other (reference) stream. Thus for cross-fading two music streams the beats of the fading-in stream can be matched to those of the fading-out stream for a seamless transition.
    Type: Grant
    Filed: September 1, 2006
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Daniel S. Jochelson, Stephen J. Fedigan
  • Patent number: 7519135
    Abstract: A radio receiver 2000 with a sampling mixer 1100 for creating a discrete-time sample stream by directly sampling an RF current with history and rotating capacitors 1111 and 1112, wherein the accumulated charge on the rotating capacitors is read-out to produce a sample. The mixer provides immunity to noise glitches by predicting the occurrence of the glitch (or detecting a significant difference between observed and predicted samples) and creating corrected samples for the corrupted samples. These corrected samples can be created with special circuitry 1933 (digital) or in the mixer 1100 (analog).
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Robert B. Staszewski, Khurram Muhammad, Kenneth J. Maggio, Dirk Leipold
  • Patent number: 7519439
    Abstract: A digital processor (2, 102) for use in a digital controller (10) is disclosed. The digital processor (2, 102) includes a coefficient product memory (22) that stores previously calculated products of filter coefficients and each of a set of available input values. The memory (22) is addressed according to a received input value, and outputs a plurality of coefficient products associated with that input value. These coefficient products are combined across time samples (with one or more coefficient products delayed for use in later cycles), to produce an output value. The digital processor (2) can be used in combination with an analog-to-digital converter (4) and a pulse-width modulated circuit (6) to control a power supply. According to another embodiment of the invention, comparators (62H, 62L) and a counter (66) can be used instead of the analog-to-digital converter, for additional efficiency.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Charles Watts, Jr.
  • Patent number: 7518346
    Abstract: A buck-boost DC/DC converter includes an inductor and a power stage having a set of switches selectively connecting the inductor between a voltage input, a voltage output and a reference level in accordance with buck or boost mode. The converter has a switch control providing control signals to the set of switches in the power stage. A comparator provides to the switch control a first pulse width modulation signal in buck mode and a second pulse width modulation signal in boost mode. A ramp generator provides to the comparator a first ramp signal for buck mode and a second ramp signal for boost mode. An overlap control provides a ramp shift signal to the ramp generator in response to a detection signal that indicates activity of the switches in the power stage. The ramp shift signal adjusts the first and second ramp signals relative to each other so as to minimize any gap and any overlap between the first and second ramp signals.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Franz Prexl, Erich Bayer, Juergen Neuhaeusler
  • Patent number: 7518997
    Abstract: Wirelessly-linked, distributed resource control (RCS1-RCSn, RCSB, RCC, ARM) supports a wireless communication system (50) for operation in non-exclusive spectrum (24-29). An available resource map (ARM) contains resource availability information gathered by mobile stations (MS1-MSn), and a wired communication channel supports sharing of resource control information among fixed-site stations (BS).
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: William R. Krenik, Carl M. Panasik, Matthew B. Shoemake
  • Patent number: 7519484
    Abstract: There is provided a power supply monitor circuit comprising a positive supply monitoring input, a negative supply monitoring input, and a voltage divider connected between the positive and negative supply monitoring inputs and having an intermediate node providing a potential intermediate those on the positive and negative supply monitoring inputs. A sampling circuit is connected to sample the potential at each of the positive supply input the negative supply input and the intermediate node. Also provided is a method of monitoring noise on a power supply whereby phase information from those samples is derived about the noise signals at the two said points.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Derek Colman, Andrew Joy, Tom Leslie
  • Patent number: 7519387
    Abstract: In order to overcome the limitation of the integrated circuit chip inter-connectability resulting from the physical dimensions of the leads, a radio frequency transmitter and/or a radio frequency receiver are included in the integrated circuit chip. Logic signal groups from one integrated circuit chip can be encoded by the modulation on the radio frequency signal and received and decoded by a second integrated circuit chip. The transmitted signal groups can be transmitted in a series format or in a parallel format. Either amplitude or frequency modulation can be used to impose information on the carrier frequency.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Nara Won
  • Patent number: 7519532
    Abstract: Transcoding from EVRC to G.729ab with LSP parameters interpolated from EVRC to G.729ab, EVRC pitch used as input to G.729ab closed-loop pitch search, and G.729ab fixed codebook pulses found from a search limited to positions of EVRC fixed codebook pulses together with positions of target-impulse correlation maxima on the subframe tracks or full track search if no EVRC pulses.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Pankaj K. Rabha
  • Patent number: 7518342
    Abstract: An apparatus for effecting power distribution to a host system at a supply locus from one of a voltage source or a battery includes: (a) a current transfer unit having a first and a second connection; the second connection being coupled with the battery; and (b) a control device switchingly coupling the first connection to effect alternating connection with the voltage source and with a low potential. The control device is sensingly coupled with the voltage source and within the apparatus for receiving indicating signals. The control device responds to the indicating signals to control the alternating connection to achieve stepped up delivery of voltage presented by the battery unit to the supply locus when the indicating signals indicate a first circumstance. The control device responds to the indicating signals to switchingly control the alternating connection to achieve charging the battery when the indicating signals indicate a second circumstance.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: John Joseph Palczynski, Jr.
  • Patent number: 7518941
    Abstract: Methods and apparatus to provide refresh for local out of range read requests for a memory device are disclosed. An example method disclosed herein provides a read signal to a memory cell. An address is received on row address lines ranging from a most significant bit row address line to a least significant bit row address line. A fixed high logic input is coupled to a first input of a row driver logic device associated with a local out of range address. Logic is provided to send a read enable signal on a bit line coupled to an output of the row driver logic device coupled to the memory cell if the address is the local out of range address.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Steven Richard Jahnke, Hiromichi Hamakawa
  • Patent number: 7519884
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 7517141
    Abstract: The present invention facilitates multi-zone furnace (102) based deposition processes by iteratively adjusting deposition time and zonal setpoint temperatures to mitigate deviations from desired target thickness(es). Coupled feedback loops are employed to update the deposition time (520) and the zonal setpoint temperatures (510) lot to lot and batch to batch while mitigating deviations fro the desired target thickness(es). Error checking is performed by computing an error metric (506) and only updating the setpoint temperatures on the error metric being within an acceptable value (508). Additionally, an excitation parameter (512) is determined that indicates variations in furnace operation.
    Type: Grant
    Filed: July 25, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Nital S. Patel, Amit M. Rajadhyaksha, James Boone
  • Patent number: 7517779
    Abstract: A method of forming an integrated circuit transistor (50). The method provides a first semiconductor region (52) and forms (110) a gate structure (54x) in a fixed position relative to the first semiconductor region. The gate structure has a first sidewall and a second sidewall (59x). The method also forms at least a first layer (58x, 60x) adjacent the first sidewall and the second sidewall. The method also forms (120) at least one recess (62x) in the first semiconductor region and extending laterally outward from the gate structure. Additional steps in the method are first, oxidizing (130) the at least one recess such that an oxidized material is formed therein, second, stripping (140) at least a portion of the oxidized material, and third, forming (160) a second semiconductor region (66x) in the at least one recess.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Lindsey H. Hall
  • Patent number: 7517640
    Abstract: The present invention provides a method for removing photoresist, and a method for manufacturing a semiconductor device. The method for removing photoresist, without limitation, may include subjecting a photoresist layer (210) located over a substrate (110) to a thermal bake (410) in the presence of hydrogen, and then removing the photoresist layer (210).
    Type: Grant
    Filed: August 11, 2005
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Donald W. Culp
  • Patent number: 7518512
    Abstract: A transponder device comprises an integrated CMOS circuit with a semiconductor substrate. A first rectifying diode (DS) is formed by the substrate diode of the CMOS circuit. A first MOS transistor structure (DR1) and a second MOS transistor structure (DR2) have their channels connected in series such that they function as a second rectifying diode, the cathode of the first rectifying diode being connected to the anode of the second rectifying diode. The first MOS transistor structure (DR1) and the second MOS transistor structure (DR2) are spaced from each other such that a distance between the two MOS transistor structures is large enough that a parasitic npn-structure formed within the substrate by the first and the second MOS structures has a negligible current gain.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventor: Ruediger Ganz
  • Patent number: 7519955
    Abstract: In a JTAG test and debug environment, the signal groups for boundary scans can have several lengths including signal groups that are longer that the shift register out. A storage unit is provided with a plurality of storage location lengths. The boundary scan signal groups are stored in a location having a suitable storage capacity. The command that transfers the boundary scan signal group includes a parameter identifying the relevant location. The scan control unit, upon receiving the command, transfers the entire boundary scan signal group as a result this command even if several transfers through the shift register out are required.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Lee A. Larson, Henry R. Hoar
  • Patent number: 7518392
    Abstract: Various systems and methods for device configuration are disclosed herein. For example, some embodiments of the present invention provide high speed pin continuity and pin-to-pin short tester circuits. Such circuits include a threshold driver, a test driver, and a comparator. An input of the threshold driver is electrically coupled to a voltage threshold, and an output of the threshold driver is electrically coupled to a test pin node via a current limiting resistor. An input of the test driver is electrically coupled to a drive data input, and an output of the test driver is electrically coupled to the test pin node. One input of the comparator is electrically coupled to the test pin node, and the other input of the comparator is electrically coupled to a threshold comparator input.
    Type: Grant
    Filed: August 2, 2006
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Gunvant T. Patel, Trevor J. Tarsi, Yun-Fu Wang, Anthony J. Lendino
  • Patent number: 7519925
    Abstract: An electronic system (10). The system comprises circuitry (P1) for receiving a system voltage from a voltage supply. The system also comprises circuitry (141), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP1) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry (221) for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry (26) for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: April 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Sami Issa, Uming Ko, David Scott