Abstract: A network element including a processor with logic for managing packet queues including a queue of free packet descriptors. Upon the transmission of a packet by a host application, the packet descriptor for the transmitted packet is added to the free packet descriptor queue. If the new free packet descriptor resides in on-chip memory, relative to queue manager logic, it is added to the head of the free packet descriptor queue; if the new free packet descriptor resides in external memory, it is added to the tail of the free packet descriptor queue. Upon a packet descriptor being requested, by a host application, to be associated with valid data to be added to an active packet queue, the queue manager logic pops the packet descriptor currently at the head of the free descriptor queue. In this manner, packet descriptors in on-chip memory are preferentially used relative to packet descriptors in external memory, thus improving system performance.

Abstract: Speckle effect in scanning display systems that employs polarized phase-coherent light is reduced by depolarizing the phase-coherent light using a depolarizer and scanning the depolarized light for producing desired images.

Abstract: A semiconductor device having a thyristor SCR with reduced turn-off time. A third semiconductor region of the second conductivity type (anode AN) and a fourth semiconductor region of the first conductivity type (anode gate AG) are formed in the top layer of a first semiconductor region; fifth semiconductor region of the first conductivity type (cathode CA) and sixth semiconductor region of the second conductivity type (cathode gate CG) are formed in the top layer of a second semiconductor region; a gate insulating film and gate electrode MG are formed on the second semiconductor region. When the thyristor is turned off from the on state, a higher potential than that on the anode is applied to the anode gate, and a diode made up of the anode and the anode gate inside the thyristor is made to conduct so as to control the potential of the anode during driving.

Abstract: A configurable voltage regulator (28; 128) operable in either of two selectable modes or topologies is disclosed. In one disclosed embodiment, the voltage regulator (28) can operate as a linear regulator or a switching regulator. A gate driver (35) and an error amplifier (36) is used in each mode. Configuration switches (34) are controlled by a configuration amplifier (40) to connect the error amplifier (36) to the gate driver (35) in the linear regulator mode, or to connect the error amplifier (36) to circuitry (42, 44, 46) for controlling the gate driver (35) in switching regulator mode. In another disclosed embodiment, the voltage regulator (128) generates a negative polarity regulated voltage according to a switching regulator or charge pump topology.

Abstract: A logic block, a cell library, a method of designing a logic block and an ASIC including the logic block. The invention provides a logic block including rows of standard cells having different track heights. In one embodiment, the invention provides a logic block including: (1) a first row of standard cells having a first track height and (2) a second row of standard cells adjacent to the first row and having a second track height that differs from the first track height.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: Provided is a method and system for reducing speckle in an image produced from a light source. The method, in one embodiment, includes providing a line generating element, the line generating element having a collection of optical elements having an axis. The method, in this embodiment, further includes directing an input beam of light at the line generating element while the line generating element is being vibrated back and forth in a direction substantially transverse to the axis.

Abstract: A method of manufacturing a semiconductor device includes forming transistors including gate electrodes and source/drain regions over a substrate. A protective layer is placed over the source/drain regions and the gate electrodes. A portion of the protective layer is removed to expose a portion of the gate electrodes. The exposed portions of the gate electrodes are amorphized, and remaining portions of the protective layer located over the source/drain regions are removed. A stress memorization layer is formed over the gate electrodes, and the substrate is annealed in the presence of the stress memorization layer to at least reduce an amorphous content of the gate electrodes. The stress memorization layer is removed subsequent to the annealing.

Abstract: A method includes generating a plurality of beams that each illuminate a separate portion of a spatial light modulator. The spatial light modulator has a first dimension of a first length and a second dimension of a second length. Each of the beams spans a portion of the first length of the first dimension and a portion of the second length of the second dimension. The method also includes scrolling the plurality of beams along the second dimension of the spatial light modulator while maintaining at least a first gap between each of the plurality of beams.

Abstract: A digital storage element (e.g., a flip-flop or a latch) comprise a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports. A clock gating element is also included that gates off a clock to the slave latch, and not the master transparent latch, based on an enable signal that is asserted to disable use of the digital storage element.

Abstract: A built-in self test unit reads tag bits of a predetermined cache entry and outputs these tag bits via an external interface. The built-in self test unit enters an emulation mode upon receipt of an emulation signal via the external interface when a first configuration register has a predetermined state. The built-in self test unit then reads tag bits upon each memory mapped read of a second configuration register. The read operation advances to next sequential tag bits upon each memory mapped read of the second configuration register. The tag bits include at least one valid bit and at least one dirty bit. The tag bits also include the most significant bits of the cached address.

Abstract: An embodiment of the invention is a method of manufacturing an integrated circuit. The method includes forming a capping layer of a back end structure (step 706), drilling an extraction line from the capping layer to an inter-metal dielectric layer (step 708), performing a supercritical fluid process to remove portions of the inter-metal dielectric layer that are coupled to the extraction line (step 710): thereby forming a denuded dielectric region. Another embodiment of the invention is an integrated circuit 2 having a back-end structure 5 coupled to a front-end structure 4. The back-end structure 5 having a first metal level 22. The first metal level 22 having metal interconnects 15 and an inter-metal dielectric layer 19. The back-end structure 5 further containing an extraction line 24 and a denuded dielectric region 25 coupled to the extraction line 24.

Abstract: A receiver which receives a stream of data packets including video data packets over a physical data link and drops data packets when an error on a physical communication layer is detected, wherein the receiver comprises a processor, configured so that it is able to check whether the received data packet is a video packet and whether it is corrupted by an error on the physical communication layer. If this is the case, the video packet is marked as corrupted and forwarded to the network layer. There is further provided a method for processing a stream of data packets including video data packets, the method including checking for each data packet whether it is a video data packet; checking for each video data packet whether it is corrupted by an error on the physical communication layer; marking a video packet as corrupted if it is corrupted due to an error on the physical communication layer; and forwarding the marked corrupted video packet to the network layer.

Abstract: A semiconductor device (100A) with plastic encapsulation compound (102) and metal sheets (103a and 104) on both surfaces, acting as heat spreaders. One or more thermal conductors (103a) of preferably uniform height connect one sheet (103b) and the chip surface (101a); the number of conductors is scalable with the chip size. Each conductor consists of an elongated wire loop (preferably copper) with the wire ends attached to a pad (105), preferably both ends to the same pad. The major loop diameter is approximately normal to the first surface and the loop vertex in contact with the sheet (103b). The substrate (104, preferably a second metal sheet) covers at least portions of the second package surface and is thermally conductively connected to the chip.

Abstract: Merging sub-resolution assist features includes receiving a mask pattern that includes the sub-resolution assist features. A first sub-resolution assist feature is selected to merge with a second sub-resolution assist feature. A merge bar width of a merge bar is established. A distance between the first sub-resolution assist feature and the second sub-resolution assist feature is determined. A merging technique is determined in accordance with the distance and the merge bar width. The first sub-resolution assist feature and the second sub-resolution assist feature are merged according to the identified merging technique.

Abstract: A novel mechanism for gain normalization of a digitally controlled oscillator (DCO) in an all digital phase locked loop (ADPLL)-based transmitter that is operative to split the gain normalization multiplication functionality between a modulating path and a PLL loop. The gain normalization of the modulation loop (referred to as modulation path multiplier) comprises a full bit resolution high precision multiplication function. The gain normalization of the PLL loop, on the other hand, is of significantly lower resolution, hence much lower complexity multiplier logic circuitry is required.

Abstract: An optical component includes a prism element adjacent to a lens element, where the two elements are separated by a small air gap. Elements of the optical component have adjacent and parallel surfaces which are substantially planar and which, with the small air gap, operate through Total Internal Reflection (“TIR”) to direct light beams that strike the planar surfaces. Light beams that strike at less than the critical angle are internally reflected, while light beams which strike at greater than the critical angle pass through. The TIR surfaces thereby separate the desired optical signals from the spurious ones. The combined TIR prism lens operates as a single and integrated component which directs desired light beams to a reflective optical processing element such as a Spatial Light Modulator and which focuses the processed light beams as they leave the combined TIR prism lens.

Abstract: Disclosed herein is a micromirror device having in-plane deformable hinge to which a deflectable and reflective mirror plate is attached. The mirror plate rotates to different angles in response to an electrostatic field established between the mirror plate and an addressing electrode associated with the mirror plate.

Abstract: Determining piece-wise polynomials which together would represent large data sets having multi-dimensional input vectors and corresponding output element. In an embodiment, a function/procedure/routine is recursively called/invoked to determine piece-wise polynomial is a data set cannot be entirely modeled by one polynomial. Another aspect of the present invention reduces the number of combinations (of orders for sub-polynomials forming the polynomials) to be tried in determining polynomials, meeting various accuracy requirements. Such a reduction is obtained based on a recognition that when the order in one dimension alone is increased and the result does not lead to acceptable accuracy of the polynomial, the combinations with a lesser number for the order (of the dimension) can be ruled out.

Abstract: The present invention provides circuitry for writing to and reading from an SRAM cell core, an SRAM cell, and an SRAM device. In one aspect, the circuitry includes a write circuit coupled to the SRAM cell core that includes at least one write transistor. The circuitry also includes a read circuit coupled to the SRAM cell core that includes at least one read transistor having a gate signal in common with the gate signal of the write transistor. The read transistor and the write transistor share a common gate signal, and each have an electrical characteristic, for which the electrical characteristic of the read transistor differs from that of the write transistor.