Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A method of making a flip chip assembly includes a substrate having a top surface and forming a plurality of generally longitudinally extending, laterally spaced apart bond fingers are formed on the top surface. Each of the plurality of bond fingers has a first longitudinal end portion and a second longitudinal end portion. Applying a transversely extending solder resist strip over the first longitudinal end portions of the bond fingers. The strip has an edge wall with a plurality of longitudinally projecting tooth portions separated by gaps. Each tooth portion and each gap aligned with a different one of the bond fingers in each adjacent pair of bond fingers.

Abstract: A metallic waveguide is mounted on a multilayer substrate. The metallic waveguide has an open end formed by a top, bottom and sides configured to receive a core member of a dielectric waveguide, and an opposite tapered end formed by declining the top of the metallic waveguide past the bottom of the metallic waveguide and down to contact the multilayer substrate. A pinnacle of the tapered end is coupled to the ground plane element, and the bottom side of the metallic waveguide is in contact with the multiplayer substrate and coupled to the microstrip line.

Abstract: Systems for channel selection in power line communications (PLC) are described. In some embodiments, a PLC device may include a processor and a memory. The memory stores instructions executable by the processor to cause the PLC device perform operations. One or more time slots in each of a plurality of frequency bands are sequentially scanned. A packet transmitted by a second PLC device to the PLC device over one of the plurality of frequency bands is detected. Additional packets received from the second PLC device are synchronized across the plurality of frequency bands based, at least in part, upon the detected packet. The additional packets are organized in a plurality of frames. Each of the plurality of frames having been transmitted by the second PLC device to the PLC device over a respective one of the plurality of frequency bands. Each frame has a plurality of time slots, and each time slot has a pair of beacon and bandscan packets.

Abstract: A semiconductor device has a leadframe with a pad and a row of elongated leads with a solderable surfaces in a common plane; a package encapsulating the leadframe with an assembled semiconductor device, leaving the common-plane lead surfaces un-encapsulated and coplanar with the package material between adjacent leads, the row of aligned leads positioned along a package edge; and grooves in the package material cut in the common-plane surface, the grooves extend along a portion of each lead length, have a width and a depth about twice the width, and expose solderable lead surfaces.

Abstract: An integrated circuit containing an NMOS transistor with a boron-doped halo is formed by co-implanting carbon in at least three angled doses with the boron halo implants. The carbon is co-implanted at tilt angles within 5 degrees of the boron halo implant tilt angle. An implant energy of at least one of the angled carbon co-implant is greater than the implant energy of the boron halo implant. A total carbon dose of the angled carbon co-implants is at least 5 times a total boron dose of the boron halo implants. The NMOS transistor has a carbon concentration in the halo regions which is at least 5 times greater than the boron concentration in the halo regions. The co-implanted carbon extends under the gate of the NMOS transistor.

Abstract: An image processing system includes a processor and optical flow determination logic. The optical flow determination logic is to quantify relative motion of a feature present in a first frame of video and a second frame of video with respect to the two frames of video. The optical flow determination logic configures the processor to convert each of the frames of video into a hierarchical image pyramid. The image pyramid comprises a plurality of image levels. Image resolution is reduced at each higher one of the image levels. For each image level and for each pixel in the first frame, the processor is configured to establish an initial estimate of a location of the pixel in the second frame and to apply a plurality of sequential searches, starting from the initial estimate, that establish refined estimates of the location of the pixel in the second frame.

Abstract: A DC-DC converter receives input power from a power source and generates a regulated DC voltage as an output. The DC-DC converter contains multiple blocks, each of which is powered by a power supply received on a supply terminal. The DC-DC converter also contains a voltage regulator to generate a lower voltage from the power source. The lower voltage generated by the regulator is provided as the power supply on the supply terminal when the regulated DC voltage is less than a reference value, and the regulated DC voltage itself is provided as the power supply on the supply terminal otherwise. The regulator is switched off when the blocks are powered by the regulated DC voltage, thereby leading to increased efficiency of the DC-DC converter.

Abstract: A circuit for detecting and correcting timing errors. A timing circuit includes an interpolator. The interpolator includes a fine counter, a coarse counter, and stop correction logic. The coarse counter is incremented by a rollover output of the fine counter to generate a coarse count value. The stop correction logic is coupled to the fine counter and the coarse counter. The stop correction logic divides each cycle of the rollover output into first, second, and third time intervals, and selects a coarse counter output value to represent a time interval measured by the coarse counter based on a one of the first, second, and third intervals in which a time measurement stop signal is detected.

Abstract: A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).

Abstract: An optimized JTAG interface is used to access JTAG Tap Domains within an integrated circuit. The interface requires fewer pins than the conventional JTAG interface and is thus more applicable than conventional JTAG interfaces on an integrated circuit where the availability of pins is limited. The interface may be used for a variety of serial communication operations such as, but not limited to, serial communication related integrated circuit test, emulation, debug, and/or trace operations.

Abstract: Adapters for electrostatic discharge probe tips are disclosed herein. An embodiment of the adapter includes an attachment device that is attachable to the tip of the probe. A first conductor is affixed to the attachment device so that the first conductor contacts the tip when the attachment device is attached to the tip of the probe. A second conductor extends between the first electrical conductor and a point external to the attachment device.

Abstract: An inductive device is provided, which includes a substrate, a layer having a plurality of conductive metal traces and a metal shield layer. The conductive trace has an input port, a first portion, a second portion, a third portion and an output port. The metal shield layer is disposed between the substrate and the conductive trace. Each of the plurality of conductive metal traces has a respective length and a respective width. Each of the plurality of conductive metal traces are separated from one another. Each of the plurality of conductive metal traces are disposed perpendicularly with the first portion and the third portion. The metal shield layer provides spaced shield traces substantially perpendicular with the conductive metal traces.

Abstract: The MSMC (Multicore Shared Memory Controller) described is a module designed to manage traffic between multiple processor cores, other mastering peripherals or DMA, and the EMIF (External Memory InterFace) in a multicore SoC. The invention unifies all transaction sizes belonging to a slave previous to arbitrating the transactions in order to reduce the complexity of the arbitration process and to provide optimum bandwidth management among all masters. Two consecutive slots are assigned per cache line access to automatically guarantee the atomicity of all transactions within a single cache line. The need for synchronization among all the banks of a particular SRAM is eliminated, as synchronization is accomplished by assigning back to back slots.

Abstract: Termination impedance of a digital signal bus is adaptively selected as a function of a present or anticipated state of the bus. A variable termination resistor is arranged in series between a termination switch and a common voltage node at the termination end of each bus conductor. Information regarding the current or anticipated bus state is received from an external device such as a bus controller or may be derived by sensing activity on the bus. For example, clock frequency detection logic coupled to clock lines of the bus senses the current operational speed of the bus. A highest-value termination resistance predetermined to be consistent with reliable bus operation under conditions of the current or anticipated bus state is selected for each bus conductor. A bus conductor termination may be taken to a high impedance state by opening the associated termination switch. Decreased average bus power consumption may result.

Abstract: The invention is directed to a method for inhibiting or preventing delamination at the interface of the die attach/mold compound and the die pad of a semiconductor device and a semiconductor device formed by such method. The method includes providing a leadframe having a top surface; coating said top surface of said leadframe with first and second silane coating; heating said silane coatings to form a sol-gel layer having a porosity of at least 10%; applying a die to said sol-gel layer; securing said die to said sol-gel layer by a die attaching compound; and after the curing of die attach material and wire bonding, a mold compound is applied through molding.

Abstract: The disclosure provides a novel method and apparatus for inputting addresses to devices to select the device TAP for access. Further, the disclosure provides a novel method and apparatus for inputting addresses for selecting device TAPs and for inputting commands for commanding circuitry within the device. The inputting of addresses or the inputting of addresses and commands is initiated by a control bit input on TDI that is recognized during the Run Test/Idle, Pause-DR or Pause-IR TAP states.

Abstract: A communication device includes a modulating component, a transmitting component and a controlling component. The modulating component generates a first modulated packet and a second modulated packet. The first modulated packet is based on a first modulation scheme and the second modulated packet is based on a second modulation scheme. The first modulation scheme has a first amount of energy associated therewith, and the second modulation scheme has a second amount of energy associated therewith. The first amount of energy is less than the second amount of energy. The transmitting component generates a transmit packet based on one of the first modulated packet and the second modulated packet. The controlling component generates a control signal to instruct the modulating component to generate the first modulated packet When the transmit packet will be less than a predetermined threshold. The threshold is based on the first amount of energy.

Abstract: A method of operating a long term evolution (LTE) communication system on a shared frequency spectrum is disclosed. A user equipment (UE) is initialized on an LTE frequency band. A base station (eNB) monitors the shared frequency spectrum to determine if it is BUSY. The eNB transmits to the UE on the shared frequency spectrum if it is not BUSY. The eNB waits for a first time if it is BUSY and directs the UE to vacate the shared frequency spectrum after the first time.

Abstract: An integrated circuit on-chip parametric (OCP) test structure includes a static random access memory (SRAM) universal test structure (UTS) having UTS ports and an OCP controller configured to determine first and second UTS ports of the SRAM UTS for independent connection to first and second on-chip test pads, respectively. The integrated circuit OCP test structure further includes a UTS OCP router connected to the OCP controller and configured to connect the first and second UTS ports of the SRAM UTS to the first and second on-chip test pads, respectively. Methods of operating an integrated circuit OCP test structure and OCP testing of an integrated circuit are also included.