Abstract: Embodiments of methods and systems are presented for generating PHY frames with multiple Reed-Solomon encoded blocks in PLC networks. In one embodiment, a MAC layer divides a data frame from a higher level into data blocks. The MAC layer may add a MAC header and/or an error-detection code to each data block. The MAC layer then passes the data blocks to a PHY layer to be individually Reed-Solomon encoded and combined into a single PHY frame for transmission on a PLC network. In other embodiments, the MAC layer passes a single data frame to the PHY layer, which divides the MAC data frame into segments to be individually Reed-Solomon encoded. The individual Reed-Solomon encoded segments are combined into a single PHY frame for transmission on a PLC network.

Abstract: A wireless device that tailors communications based on power parameters of the device. In one embodiment, a wireless device includes an energy source, a power monitor coupled to the energy source, a wireless transceiver, and a traffic controller coupled to the power monitor and the wireless transceiver. The power monitor is configured to measure a parameter of the energy source. The wireless transceiver is configured to wirelessly communicate via a wireless network. The traffic controller is configured to set length of packets to be transmitted based on the measured parameter of the energy source.

Abstract: A system includes an analog front end (AFE) unit to be coupled to a power line network, and a controller coupled to the AFE unit. More specifically, the AFE unit is to receive a packet signal from the power line network wherein, based on a first gain parameter, the AFE unit is to amplify the received packet signal. The controller is configured to calculate a root-mean-square (RMS) power of the amplified packet signal. Further, the AFE unit is to calculate a second gain parameter based on the calculated RMS power of the amplified packet signal and the first gain parameter, wherein the second gain parameter is to be used to amplify the received packet signal instead of the first gain parameter.

Abstract: An integrated circuit has two parallel digital transistors and a perpendicular analog transistor. The digital transistor gate lengths are within 10 percent of each other and the analog gate length is at least twice the digital transistor gate length. The first digital transistor and the analog transistor are implanted by a first LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the first digital transistor gate edge and parallel to the analog transistor gate edge. The second digital transistor and the analog transistor are implanted by a second LDD implant which includes a two sub-implant angled halo implant process with twist angles perpendicular to the second digital transistor gate edge and parallel to the analog transistor gate edge. The first halo dose is at least 20 percent more than the second halo dose.

Abstract: One embodiment of the invention includes a battery sense system. The system includes a temperature sensor configured to measure a temperature of a battery and a memory configured to store predetermined data associated with steady-state and transient behaviors of the battery relative to a depth of discharge (DOD) of the battery. The system also includes a controller configured to measure a voltage of the battery and to calculate a state of charge (SOC) of the battery based on the voltage, the predetermined data, and the temperature.

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Abstract: A wireless device includes a wireless transceiver configured to transmit to and receive from nodes in a wireless sensor network (WSN) and control logic coupled to the first wireless transceiver. The wireless transceiver transmits a wireless packet to a node in the WSN based on the transmission coinciding with a break in transmissions for a second wireless network. Based on the wireless transceiver being configured to transmit the wireless packets utilizing time synchronized channel hopping, slot frames for packet transmissions in the WSN are time offset so as not to coincide with transmissions made on the second wireless network. Based on the wireless transceiver being configured to transmit the packets utilizing coordinated sampled listening, wake up sequence transmissions for the WSN are time offset so as not to coincide with the transmissions made on the second wireless network.

Abstract: An integrated circuit package having a die attach paddle, a power die mounted on the die attach paddle and a controller die mounted on the die attach paddle. The die attach paddle has at least one recessed portion at least partially underlying the controller die.

Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.

Abstract: An LLC converter having a bridge circuit coupled to an input voltage at least one pair of power switches, a resonant network, coupled to the bridge circuit and driven by power switches, an output transformer coupled to the resonant network having first and second primary side windings and a secondary side winding, a current sense transformer on the primary side in series to the resonant network and the first primary winding, an integrator circuit coupled in parallel to the second primary side winding and in parallel to the secondary side winding of the current sense transformer the transformer providing an output current of the LLC series resonant converter and a frequency adjustment controller coupled to at least one pair of power switches and the current sense transformer and the integrator circuit providing driving signals to the at least one pair power switches.

Abstract: A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract: A material-discerning proximity sensor is arranged to include an antenna that is arranged to radiate a radio-frequency signal. A capacitive sensor is arranged to detect a change in capacitance of the capacitive sensor and to receive the radio-frequency signal. An electrical quantity sensor is arranged to detect a change of the received radio-frequency signal.

Abstract: Read margin measurement circuitry for measuring the read margin of floating-gate programmable non-volatile memory cells. In some embodiments, the read margin of a cell with a floating-gate transistor in a non-conductive state is measured by periodically clocking a counter following initiation of a read cycle; a latch stores the counter contents upon the cell under test making a transition due to leakage of the floating-gate transistor. Logic for testing a group of cells in parallel is disclosed. In some embodiments, the read margin of a cell in which the floating-gate transistor is set to a conductive state is measured by repeatedly reading the cell, with the output developing a voltage corresponding to the duty cycle of the output of the read circuit.

Abstract: A system includes multiple power supplies connected in series and an active balancing circuit. The active balancing circuit includes an LC resonance circuit and multiple switches configured to selectively couple different ones of the power supplies to the LC resonance circuit. The LC resonance circuit includes an inductor, a capacitor, and an additional switch. The inductor is configured to store energy to be transferred between two or more of the power supplies. The additional switch is configured to selectively create a resonance between the inductor and the capacitor in order to reverse a direction of a current flow through the inductor. The active balancing circuit can transfer energy between individual power supplies or groups of power supplies.

Abstract: An integrated circuit includes a PMOS gate structure and a gate structure on adjacent field oxide. An epitaxy hard mask is formed over the gate structure on the field oxide so that the epitaxy hard mask overlaps the semiconductor material in PMOS source/drain region. SiGe semiconductor material is epitaxially formed in the source/drain regions, so that that a top edge of the SiGe semiconductor material at the field oxide does not extend more than one third of a depth of the SiGe in the source/drain region abutting the field oxide. Dielectric spacers on lateral surfaces of the gate structure on the field oxide extend onto the SiGe; at least one third of the SiGe is exposed. Metal silicide covers at least one third of a top surface of the SiGe. A contact has at least half of a bottom of the contact directly contacts the metal silicide on the SiGe.

Abstract: Methods, computer-readable media, and systems for virtual memory management using the JAVA programming language are provided. In some illustrative embodiments, a computer-readable medium storing a program that, when executed by a processor, performs a method for virtual memory management is provided. The method includes creating a representation of a page table, wherein each entry of the representation comprises a representation of a page descriptor, changing a field of a representation of a page descriptor in the representation of the page table, and updating a corresponding field in a page descriptor of a system level page table using the contents of the field in the representation of the page descriptor.

Abstract: Described examples include DC-DC power conversion systems, apparatus and methods for linearizing a DC-DC circuit conversion gain, including a gain circuit providing an output signal according to a gain value and the difference between a first compensation signal and a threshold signal, and a switching circuit selectively operative when the first compensation signal exceeds the threshold signal to linearize the conversion gain by providing a second compensation signal for pulse width modulation of at least one DC-DC converter switch according to the threshold signal and the gain circuit output signal.

Abstract: A semiconductor device includes at least a first transistor including at least a second level metal layer (second metal layer) above a first level metal layer coupled by a source contact to a source region doped with a first dopant type. The second level metal layer is coupled by a drain contact to a drain region doped with the first dopant type. A gate stack is between the source region and drain region having the second level metal layer coupled by a contact thereto. The second level metal layer is coupled by a contact to a first isolation region doped with the second dopant type. The source region and drain region are within the first isolation region. A second isolation region doped with the first dopant type encloses the first isolation region, and is not coupled to the second level metal layer so that it electrically floats.

Abstract: DC-DC converter PWM controllers and dual counter digital integrators are presented for integrating an error between a reference voltage signal and a feedback voltage signal, in which a comparator, dual counters, and a DAC are used to provide a compensated reference to a modulator loop comparator which generates a PWM switching signal for controlling a power converter output voltage, with the second counter being selectively incremented or decremented when the first counter output indicates a predetermined value after the first counter output transitions in one direction through a predetermined count range to enhance loop stability, and a startup mode control allows fast integrator operation during initialization, with the ability to freeze integrator operation during overcurrent conditions.