Abstract: A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal interconnect layer which provides a plurality of bond pads that are coupled to circuit nodes on the IC device. The plurality of bond pads include a metal bond pad area. At least one passivation layer provides a trench including dielectric sidewalls above the metal bond pad area. A ruthenium (Ru) layer is deposited directly on the dielectric sidewalls and directly on the metal bond pad area, which removes the need for a barrier layer lining the dielectric sidewalls of the trench. The Ru layer is patterned to provide a bond pad surface for the plurality of bond pads.

Abstract: A method is shown to provide remote access to one or more debug access points whose functions include capabilities other than accessing memories across an application interface such as USB, IEEE 802.3 (Ethernet) and other protocols. The capabilities available include all or many of the capabilities provided by a dedicated debug interface.

Abstract: In ACK/NAK responses with repetition, the ACK/NAK response from the user equipment to a Physical Downlink Shared CHannel (PDSCH) transmission is repeated in consecutive frames a predetermined number of frames following receipt. This repeat ACK/NAK causes a problem when a PSCCH transmission directed to the same user equipment occurs in consecutive subframes. In a first embodiment, the first ACK/NAK response repeats preempting any ACK/NAK response to the later PDSCH transmission. In a second embodiment, the first ACK/NAK response does not repeat and the ACK/NAK response to the later PDSCH transmission occurs.

Abstract: The present invention provides method and apparatus for adapting a relatively high data rate second order serdes receiver to receive relatively low data rate serial data, the receiver having jog realignment by and having means for receiving the serial data as a plurality of repeated bits at the high data rate; framing the data as frames of repeated bits of the same value; examining the bits of the frame for the presence of bits which are not of the same value; upon detecting such a presence that is indicative of a framing error jogging the serdes receiver for frame realignment; and supplying to an output of the serdes receiver one of the bits of said same value from each frame at the low data rate.

Abstract: A MEMS mixer filter including an array of a multiplicity of resonator elements with conductive outer surfaces in a coplanar rectangularly tiled array, and two sets of DC bias lines in which alternating resonator elements in each row and column are connected to one or the other sets of bias lines so that laterally adjacent resonators may be biased to a DC potential. The resonator elements are uniform in size and shape. Lateral dimensions of the resonator elements are between 5 and 50 microns. The resonator elements are between 100 nanometers and 100 microns thick, and adjacent resonator elements are separated by a gap between 100 and 500 nanometers. A process of forming the MEMS mixer filter.

Abstract: An integrated circuit has controller circuitry having coupled to a test clock and a test mode select inputs, and having state a register clock state output, a register capture state output, and a register update state output. Register circuitry has a test data in lead input, control inputs coupled to the state outputs of the controller circuitry, and a control output. Connection circuitry has a control input connected to the control output of the register circuitry and selectively couples one of a first serial data output of first scan circuitry and a second serial data output of second scan circuitry to a test data out lead. Selection circuitry has an input connected to the serial data input lead, an input connected to a test pattern source lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

Abstract: A lid comprising a heat conductive substrate and a native silicon oxide layer connected to said substrate by at least one intermediate layer; a lidded integrated circuit package; and a method of providing a heat path through an integrated circuit package comprising providing a substrate with an exterior layer of native silicon oxide and interfacing the layer of native silicon oxide with a layer of thermal interface material.

Abstract: An apparatus for mapping data in a wireless communication system. The apparatus includes circuitry for generating a precoding matrix for multi-antenna transmission based on a precoding matrix indicator (PMI) feedback from at least one remote receiver where the PMI indicates a choice of precoding matrix derived from a matrix multiplication of two matrices from a first code book and a second codebook. The apparatus further includes circuitry for precoding one or more layers of a data stream with the precoding matrix and transmitting the precoded layers of data stream to the remove receiver.

Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.

Abstract: An integrated circuit containing a PMOS transistor may be formed by implanting boron in the p-channel source drain (PSD) implant step at a dose consistent with effective channel length control, annealing the PSD implant, and subsequently concurrently implanting boron into a polysilicon resistor with a zero temperature coefficient of resistance using an implant mask which also exposes the PMOS transistor, followed by a millisecond anneal.

Abstract: The present invention provides a means for optimization and re-use of hardware in the implementation of Viterbi and Turbo Decoders using carry save arithmetic. Successful provision for each target application requires that two main issues be confronted. These are: merging the computation of summation terms (a2?b2+c2) with (x2+y2+z2); and (a3+b3?c3) with (x3+y3+z3); implementing an efficient method of computing (a4?b4?c4); and merging this computation with (x4+y4+z4). The invention solves both of these issues and successfully merges the Viterbi instructions with a complete reuse of the hardware that is required for the implementation of Turbo instructions. The hardware required by both classes of instructions is optimized by efficiently employing carry save arithmetic.

Abstract: The invention relates to a semiconductor device and a method of manufacturing an electronic device. A first conductive layer (first metal interconnect layer) is deposited. There is an insulating layer (first intermetal dielectric) layer deposited. A resistive layer is deposited on top of the insulating layer and structured in order to serve as a thin film resistor. A second insulating layer (second intermetal dielectric) is then deposited on top of the resistive layer. A first opening is etched into the insulating layers (first and second intermetal dielectric) down to the first conductive layer. A second opening is etched into the insulating layers (first and second intermetal dielectrics) down to the first conductive layer. A cross-sectional plane of the second opening is arranged such that it at least partially overlaps the resistive layer of the thin film resistor in a first direction.

Abstract: This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.

Abstract: A method of displaying an image includes alternating an active state of each of a plurality of light sources. The light sources each generate a light beam when active. The alternating includes deactivating an active light source before an output of a light beam from the active light sources falls below a first predetermined threshold. The alternating further includes activating a deactivated light source only after an output of the inactive light source reaches a second predetermined threshold. The method further includes receiving each of the light beams at a spatial light modulator.

Abstract: An apparatus for concurrent test of a set of flash memory banks apparatus includes a memory data path (MDP) module coupled to a test controller. The MDP module includes a test control module configured to generate a concurrent control signal that configures the set of flash memory banks to be tested simultaneously; and a set of comparators, that generates a first comparator output in response to the concurrent control signal and an input from the set of flash memory banks. A reduction logic is configured to generate a reduction logic output that combines a status of the comparator outputs to be compressed. A control logic is configured for selective programming across different flash bits of the set of flash memory banks. A fail flag is configured to generate one of an output value ‘0’ if there is a mismatch in data read from the set of flash memory banks in any access, and an output value 1 if there is no mismatch in data read in any access.

Abstract: A tunable DCO (digitally controlled oscillator), for example, includes a clock generator that is arranged to provide a converter clock signal for driving a frequency-to-voltage (F2V) converter. The F2V converter, for example, includes a frequency target control input for selecting an operational frequency and in response generates a frequency control signal using a DAC (digital-to-analog converter). The example F2V converter is arranged using a split capacitor DAC to provide a linear voltage response over a range of trim codes. The clock generator is arranged to generate the converter clock signal in response to the frequency control signal.

Abstract: Circuits and methods for controlling electrical coupling by a load switch are disclosed. In an embodiment, the load switch includes a pass element, level-shift circuit and low-resistance active path. The pass element is configured to be coupled to a power supply and a load, and is configured to electrically couple the power supply with the load during ON-state and electrically decouple the power supply from the load during OFF-state. The level-shift circuit includes a first transistor and pull-up resistor and is configured to generate a level-shifted signal in response to an enable signal, and enable the ON-state and the OFF-state of the pass element based on first and second voltages of the level-shifted signal. The low-resistance active path is coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state by providing a path for a leakage current of the first transistor in the OFF-state.

Abstract: In an embodiment of the invention, a storage element which provides a user program is extended by logic which can detect special conditions and inject special start addresses on demand. During the read (fetch) of a start address of the user program, which is always at a fixed address for a given CPU, the conditions are used to respond to this read address either by different hardcoded addresses or by the original content of the memory.

Abstract: An embodiment provides a circuit for testing an integrated circuit. The circuit includes an input converter that receives N scan inputs and generates M pseudo scan inputs, where M and N are integers. A scan compression architecture is coupled to the input converter and generates P pseudo scan outputs in response to the M pseudo scan inputs. An output converter is coupled to the scan compression architecture and generates Q scan outputs in response to the P pseudo scan outputs, wherein P and Q are integers. The input converter receives the N scan inputs at a first frequency and generates the M pseudo scan inputs at a second frequency and the output converter receives the P pseudo scan outputs at the second frequency and generates the Q scan outputs at the first frequency.

Abstract: A fractional-N frequency synthesizer that suppresses integer boundary spurs. A frequency synthesizer includes a fractional-N phase locked loop (PLL) and a reference frequency scaler. The reference frequency scaler is coupled to a reference clock input of the PLL, the reference frequency scaler includes a programmable frequency divider, and a programmable frequency multiplier connected in series with the programmable frequency divider. Each of the divider and multiplier is configured to scale a reference frequency provided to the PLL by a programmable integer value.