Abstract: An integrated circuit containing an analog MOS transistor may be formed by implanting drain extensions with exactly four sub-implants wherein at least one sub-implant implants dopants in a substrate of the integrated circuit at a source/drain gate edge of the analog MOS transistor at a twist angle having a magnitude of 5 degrees to 40 degrees with respect to the source/drain gate edge of the analog MOS transistor, for each source/drain gate edge of the analog MOS transistor, wherein a zero twist angle sub-implant is perpendicular to the source/drain gate edge. No more than two sub-implants put the dopants in the substrate at any source/drain gate edge of the analog MOS transistor. All four sub-implants are performed at a same tilt angle. No halo implants are performed on the analog MOS transistor.

Abstract: Single user and multiuser MIMO transmission in a cellular network may be performed by selecting by a base station (eNB) to transmit either one or two transmission layers. When one transmission layer is selected, a first transmission layer is precoded with a first precoder. A first demodulation reference signal (DMRS) sequence or a second DMRS sequence is selected by the eNB and precoded using the first precoder. The first transmission layer is transmitted with the selected precoded DMRS from the eNB to a user equipment (UE), and an indicator is transmitted to the UE to indicate which DMRS sequence is selected and transmitted.

Abstract: Screening a batch of integrated circuits (IC) may be done with test patterns provided in a sequence of test vectors. The sequence of test vectors may be fetched from a memory coupled to a tester and then one or more bits from each test vector may be provided to the tester. A test pattern is formed by updating a latch in a periodic manner with a bit value from a same bit position from each of the sequence of test vectors. The test pattern may then be applied to an input pin of a device under test and a resulting signal may be monitored on an output pin of each one of the batch of ICs. A slow speed ICs may be screened by treating each IC that passes both a fast pattern test and a slow speed pattern test as a failure, for example.

Abstract: A semiconductor device has an n-type buried layer formed by implanting antimony and/or arsenic into the p-type first epitaxial layer at a high dose and low energy, and implanting phosphorus at a low dose and high energy. A thermal drive process diffuses and activates both the heavy dopants and the phosphorus. The antimony and arsenic do not diffuse significantly, maintaining a narrow profile for a main layer of the buried layer. The phosphorus diffuses to provide a lightly-doped layer several microns thick below the main layer. An epitaxial p-type layer is grown over the buried layer.

Abstract: A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.

Abstract: A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A memory protection unit including hardware logic. The hardware logic receives a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated with a virtual CPU identification (ID), wherein the virtual CPU is implemented on a physical CPU. The hardware logic also determines whether to grant or deny access to the bus slave based on the virtual CPU ID. The virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

Abstract: A method includes searching a plurality of lines of a log file for a violation of a defined condition; creating a database of all discovered violations; converting the database of all discovered to a list of output violations grouped by master; and producing a condensed summary of error messages, the producing including: searching for a selected error message; extracting a single instance or error message and load into a master log file; searching for all other examples at all levels of a hierarchical output of the list; writing a count of instances of the violation messages to the master log file; and presenting a single instance of the violations, and the count of that violation.

Abstract: A power line communication (PLC) device comprises a processor and a memory coupled to the processor. The memory is configured to store program instructions executable by the processor to cause the PLC device perform operations. One or more time slots are sequentially scan in each of a plurality of frequency bands. A packet transmitted by a second PLC device to the PLC device over one of the plurality of frequency bands is detected. Additional packets received from the second PLC device across the plurality of frequency bands based, at least in part, upon the detected packet are synchronized. The additional packets are organized in a plurality of frames, each of the plurality of frames having been transmitted by the second PLC device to the PLC device over a respective one of the plurality of frequency bands.

Abstract: An apparatus includes a vapor cell having multiple cavities fluidly connected by one or more channels. At least one of the cavities is configured to receive a first material able to dissociate into one or more gases that are contained within the vapor cell. At least one of the cavities is configured to receive a second material able to absorb at least a portion of the one or more gases. The vapor cell could include a first cavity configured to receive the first material and a second cavity fluidly connected to the first cavity by at least one first channel, where the second cavity is configured to receive the gas(es). The vapor cell could also include a third cavity fluidly connected to at least one of the first and second cavities by at least one second channel, where the third cavity is configured to receive the second material.

Abstract: A method for fabricating a semiconductor proximity sensor includes providing a flat leadframe with a first and a second surface. The second surface is solderable. The leadframe includes a first and a second pad, a plurality of leads, and fingers framing the first pad. The fingers are spaced from the first pad by a gap which is filled with a clear molding compound. A light-emitting diode (LED) chip is assembled on the first pad and encapsulated by a first volume of the clear compound. The first volume outlined as a first lens. A sensor chip is assembled on the second pad and encapsulated by a second volume of the clear compound. The second volume outlined as a second lens. Opaque molding compound fills the space between the first and second volumes of clear compound, forms shutters for the first and second lenses, and forms walls rising from the frame of fingers to create an enclosed cavity for the LED.

Abstract: Within a display area of a touchscreen, multiple elements are displayed. A location is detected of a physical touch within the display area. In response to determining that an ambiguity exists about which of the elements is being targeted by the physical touch, a menu is displayed on the touchscreen for prompting a user to select between ones of the elements that are at least partially displayed within a specified area around the location. The ambiguity is resolved by receiving a selection from the user via the menu.

Abstract: A device and method for controlling radio power in a wireless sensor network. A wireless sensor device includes a wireless transceiver, a white list generator, and power control logic. The wireless transceiver is configured to transmit and receive via a wireless sensor network. The white list generator configured to identify wireless sensor nodes that communicate directly with the wireless sensor device via the wireless sensor network, to identify time slots assigned for communication between the wireless sensor device and each of the identified wireless sensor nodes, and to create and maintain a list of the identified wireless sensor nodes and corresponding time slots. The power control logic is configured to power the transceiver for reception of transmissions from each identified wireless sensor node based on the identified time slots corresponding to the identified wireless sensor node provided in the list.

Abstract: An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell. A method for forming an integrated circuit with DSL borders perpendicular to the tranistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates primarily outside the nwell.

Abstract: A process and apparatus provide a JTAG TAP controller (302) to access a JTAG TAP domain (106) of a device using a reduced pin count, high speed DDR interface (202). The access is accomplished by combining the separate TDI and TMS signals from the TAP controller into a single signal and communicating the TDI and TMS signals of the single signal on the rising and falling edges of the TCK driving the DDR interface. The TAP domain may be coupled to the TAP controller in a point to point fashion or in an addressable bus fashion. The access to the TAP domain may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.

Abstract: An integrated circuit may include an over-capability detection circuit coupled to an I/O pad which provides a shut-off signal to a latch controlling an ESD protection shunting component. The ESD protection shunting component is coupled between the I/O pad and a reference node of the integrated circuit. The over-capability detection circuit provides the shut-off signal when safe operating conditions are resumed after a voltage excursion at the I/O pad. After receiving the shut-off signal, the latch biases the ESD protection shunting component into an off-state.

Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).

Abstract: The invention is a method of operating a system having multiple finite state machines and a controller. Each finite state machine enters an offline state upon detection of anomalous operation. The controller detects whether all finite state machines are offline. The controller transmits an online activation event signal to each finite state machine when all are offline. Each finite state machine evaluates entering the online state if current conditions permit. Reentering the online state includes loading a predetermined set of operating parameters. The finite state machines are responsive only to a reset event and an online activation event when in the offline state.

Abstract: Several circuits and methods implemented to perform signal quality estimation and control are disclosed. In an embodiment, a method of signal quality estimation includes generating a demodulated signal associated with a radio signal. Information associated with a quality of the demodulated signal is accessed. Further, a value of radio frequency signal-to-noise ratio (RF-SNR) for the radio signal based on the information is estimated. Estimating the value of RF-SNR facilitates in signal quality estimation of the radio signal and control of the demodulated signal.