Abstract: A system can include a close-in tone control configured to detect a set of close-in tones of an interleaved analog to digital converter (IADC) signal and output a trigger signal in response to the detection. The system can also include a close-in tone mismatch estimator configured to determine a correlation and a power estimate for the set of close-in tones in the IADC signal in response to the trigger signal.

Abstract: An image input/output apparatus and method includes a light source in optical communication with a spatial radiation modulator for projecting an output image and an image sensor for capturing an input image along a shared input/output path. In a described embodiment, the display of an output image and the capture of an input image is effected using a common spatial radiation modulator (SRM) in the form of a deformable mirror device (DMD).

Abstract: Systems and methods for implementing coexistence by requesting access to a channel in power line communications (PLC) are described. In an illustrative embodiment, a method performed by a PLC device, such as a PLC meter, may include detecting a communication from foreign PLC device on a PLC network in response to a foreign preamble received by the PLC device, determining whether a threshold back-off duration has been reached, and transmitting a channel access request in response to a determination that the threshold back-off duration has been reached.

Abstract: A mixed signal approach is applied to detect an output voltage condition as applied to a load. A current mode monitoring approach can be adopted and applied in discrete time using a mixed analog and digital approach. For application to various low drop-out voltage regulator situations, a sensing transistor can be connected in parallel with a feedback loop transistor of the low drop-out voltage regulator circuit to create a sensing current that is proportional to the current passing through the feedback loop transistor and thus the output current provided to the load. This sensing approach can be adapted to sense both overload and light load conditions to allow dynamic power control of the device.

Abstract: An integrated circuit is provided with a bandgap voltage reference circuit having a bandgap reference voltage output. A bandgap failure detection circuit is coupled to the bandgap reference voltage output. The bandgap failure detection forms a model value of the reference voltage from a first time, compares a present value of the reference voltage at a second time to the model value; and asserts a bandgap fail signal to indicate when the present value is less than the model value by a threshold value. The integrated circuit is reset by the bandgap fail signal. The detection circuit may be operated from a failsafe voltage domain that also allows a critical circuit to complete a pending operation during a reset.

Abstract: A photodetector detects the absence or presence of light by detecting a change in the inductance of a coil. The magnetic field generated when a current flows through the coil passes through an electron-hole generation region. Charged particles in the electron-hole generation region come under the influence of the magnetic field, and generate eddy currents whose magnitudes depend on whether light is absent or present. The eddy currents generate a magnetic field that opposes the magnetic field generated by current flowing through the coil.

Abstract: An inverter type level shifter includes a first power supply voltage and a first ground voltage. A first inverter operates on the first power supply voltage and the first ground voltage to generate a first inverter output. The first inverter includes a first PMOS transistor having a drain coupled to a source of a blocking PMOS transistor and a first NMOS transistor having a drain coupled to a source of a blocking NMOS transistor. The level shifter further includes a second power supply voltage and a second ground voltage, and a second inverter coupled to the first inverter output and operates on the second power supply voltage and the second ground voltage. The blocking PMOS provides the required blocking on the event of the voltage spike in the second power supply voltage w.r.t the first power supply voltage and the blocking NMOS transistor provides the required blocking on the event of the voltage spike in the second ground voltage with respect to the first ground voltage.

Abstract: Embodiments of the present disclosure provide a transmitter, a receiver and methods of operating a transmitter and a receiver. In one embodiment, the transmitter includes a synchronization unit configured to provide a primary synchronization signal and a secondary synchronization signal having first and second segments. The transmitter also includes a secondary scrambling unit configured to provide a scrambled secondary synchronization signal, wherein scrambling agents for the first and second segments are derived from a primary synchronization sequence of the primary synchronization signal. The secondary scrambling unit is further configured to provide an additional scrambling of one of the first and second segments, wherein a second scrambling agent is derived from the remaining segment of a secondary synchronization sequence of the secondary synchronization signal.

Abstract: In at least some embodiments, a communication device includes a transceiver with a physical (PHY) layer. The PHY layer is configured for body area network (BAN) operations in a limited multipath environment using M-ary PSK, differential M-ary PSK or rotated differential M-ary PSK. Also, the PHY layer uses a constant symbol rate for BAN packet transmissions.

Abstract: A video system includes an encoder for generating a compressed bit stream in response to a received video signal. A transitional location is located in the bit stream that includes skip macro-block encoding, where the transitional location provides an indication where a linear relationship starts to exist between a length of the encoded bit stream and a length of a number of skipped macro-blocks. The skipped macro-blocks in the bit stream before the transitional location are encoded using a predetermined nonlinear relationship between the length of the encoded bit stream and the length of the number of skipped macro-blocks, whereas skipped macro-blocks in the bit stream are encoded using a linear relationship between the length of the encoded bit stream and the length of the number of skipped macro-blocks.

Abstract: Scratch pad register banks are used as shared fast access storage between processors in a multi processor system. Instead of the usual one to one register mapping between the processors and the scratch pad register banks, an any to any mapping is implemented. The utilization of the scratch pad register banks is improved as the any to any mapping of the registers allow the storage of any processor register anywhere in the scratch pad register bank.

Abstract: An IC processor circuit has an interface for a microphone and a packet switched network. A memory holds bits for converting audible speech from the microphone into digital data in each of successive frames. For each frame the converting includes forming LPC data, LTP lag data, parity check data, adaptive and fixed codebook gain data, and fixed codebook pulse data. The digital data representing the audible speech for the frames is placed into sequential packets, with each packet having a primary stage and a secondary stage. The placing includes arranging data from a first frame of speech in the primary stage of a first packet and arranging data from the first frame of speech in the secondary stage of a second packet, which follows the first packet. The data in the secondary stage includes only LPC data, LTP lag data, parity check data, and adaptive and fixed codebook gain data.

Abstract: A device has a microelectromechanical system (MEMS) component with at least one surface and a coating disposed on at least a portion of the surface. The coating has a compound of the formula M(CnF2n+1Or), wherein M is a polar head group and wherein n?2r. The value of n may range from 2 to about 20, and the value of r may range from 1 to about 10. The value of n plus r may range from 3 to about 30, and a ratio of n:r may have a value of about 2:1 to about 20:1.

Abstract: A video encoder receives a macro-block of an image frame, and determines whether the macro-block contains text. The video encoder computes a quantization parameter for quantizing the macro-block, with the quantization parameter computed to be smaller if the macro-block is determined to contain text. The video encoder encodes the macro-block using the quantization parameter. Text quality in the encoded macro-block is preserved.

Abstract: A segmented bipolar transistor includes a p-base in a semiconductor surface including at least one p-base finger having a base metal/silicide stack including a base metal line that contacts a silicide layer on the semiconductor surface of the p-base finger. An n+ buried layer is under the p-base. A collector includes an n+ sinker extending from the semiconductor surface to the n+ buried layer including a collector finger having a collector metal/silicide stack including a collector metal line that contacts a silicide layer on the semiconductor surface of the collector finger. An n+ emitter has at least one emitter finger including an emitter metal/silicide stack that contacts the silicide layer on the semiconductor surface of the emitter finger. The emitter metal/silicide stack and/or collector metal/silicide stack include segmentation with a gap which cuts a metal line and/or the silicide layer of the stack.

Abstract: This patent application considers the configuration aperiodic sounding reference signal parameters by radio resource control signaling and the triggering of aperiodic SRS transmission by detection of a positive trigger in downlink control information. Transmission timing rules are also proposed to determine the valid subframes for aperiodic SRS transmission.

Abstract: To enable efficient tracking of transactions, an acknowledgement expected signal is used to give the cache coherent interconnect a hint for whether a transaction requires coherent ownership tracking. This signal informs the cache coherent interconnect to expect an ownership transfer acknowledgement signal from the initiating master upon read/write transfer completion. The cache coherent interconnect can therefore continue tracking the transaction at its point of coherency until it receives the acknowledgement from the initiating master only when necessary.

Abstract: A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.

Abstract: A method and apparatus for Time Of Flight sensor 2-dimensional and 3-dimensional map generation. The method includes retrieving Time Of Flight sensor fixed point data to obtain four phases of Time Of Flight fixed point raw data, computing Gray scale image array and phase differential signal arrays utilizing four phases of TOF fixed point raw data, computing Gray image array and Amplitude image array for fixed point, converting the phase differential signal array from fixed point to floating point, performing the floating point division for computing Arctan, TOF depthmap, and 3-dimensional point cloud map for Q format fixed point, and generating depthmap, 3-dimensional cloud coefficients and 3-dimensional point cloud for Q format fixed point.

Abstract: A method and apparatus for encoding video data. At least a portion of a two dimensional array of transform coefficients representing a portion of video data is re-ordered to a one dimensional array of data by diagonally scanning the portion in at least two scan lines. Each scan line directed in a single common diagonal direction. Syntax elements representing at least a portion of the one dimensional array of data are then coded and transmitted.