Abstract: A tray loading system for tested electronic components including a tray loading bin adapted to prevent trays of a first configuration from being operably received in a first bin operating mode and to operably receive trays of the first configuration in a second bin operating mode. The system also includes an operating mode switching assembly adapted to automatically change from the second operating mode to the first operating mode in response to an operation associated with removal of loaded trays of the first configuration from the tray loading bin.

Abstract: An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.

Abstract: An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

Abstract: A method of forming a functionalized sensor array includes providing a substrate having at least one sensor array chip including a plurality of sensor structures. The sensor structures include a piezoelectric layer interposed between upper and lower electrodes and positioned across an area of the sensor array chip in a spatial arrangement. An inkjet cartridge chip is also provided having a plurality of microfluidic channels including a fill side having a plurality of fill side orifices and a dispense side having a plurality of dispense nozzles, wherein two or more of the plurality of microchannels are loaded with different sensing materials, and wherein locations of the plurality of dispense nozzles are matched to the spatial arrangement. The plurality of dispense nozzles are aligned to the plurality of sensor structures, and the plurality of dispense nozzles are actuated to deposit the different sensing materials on the plurality of sensor structures.

Abstract: An integrated circuit is formed by forming an isolation mesa over a single crystal substrate which includes silicon, and forming a first epitaxial layer on the substrate by a selective epitaxial process so that a top surface of the first epitaxial layer is coplanar with the top surface of the isolation mesa. A non-selective epitaxial process forms single-crystalline silicon-based semiconductor material on the first epitaxial layer and non-crystalline silicon-based material on the isolation mesa. A cap layer is formed over the second epitaxial layer, and a radiantly-induced recrystallization process causes the non-crystalline silicon-based material to form single-crystalline semiconductor over the isolation mesa.

Abstract: An integrated circuit (“IC”) package strip support assembly for a saw table including a first material having a first hardness and having a surface adapted to engage a first surface of an IC package strip during sawing; and a second material having a second hardness and having a surface adapted to engage the first surface of the IC package strip during sawing wherein the second hardness is less than the first hardness.

Abstract: A method of encoding a coding unit of a digital video sequence is provided that includes computing a brightness measure for each region in a plurality of regions in the coding unit, wherein the brightness measure indicates a relative brightness between the region in the coding unit and a corresponding region in a reference coding unit, determining a number of regions in the plurality of regions with significant brightness change by comparing each brightness measure to a region brightness change threshold, detecting whether there is global brightness change in the coding unit by comparing the number of regions to a global brightness threshold, and when global brightness change is detected, computing weighted prediction factors to be used for weighted prediction in encoding the coding unit.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: Inductive position sensing uses inductance multiplication with series connected sensor coils. In one embodiment, a first sensing domain area is established in a first target plane using first and second sensor coils disposed on a longitudinal axis, on opposite sides of the first target plane and connected in series, so that a series-combined inductance is a multiple of a sum of the respective first and second coil inductances. Target position within the first sensing domain area of the first target plane is detected based on the series-combined inductance of the first and second coils, which changes as the target moves within the first sensing domain area of the first target plane. Further sensitivity can be achieved by additional coils, series connected on the same longitudinal axis, each coil pair defining a sensing area on a respective target plane intermediate the coils.

Abstract: Embodiments of the present disclosure provide a reporting allocation unit, an indicator interpretation unit and methods of operating a reporting allocation unit and an indicator interpretation unit. In one embodiment, the reporting allocation unit includes an indicator configuration module configured to provide reporting interval and offset values of corresponding rank and channel quality indicators for user equipment. The reporting allocation unit also includes a sending module configured to transmit the reporting interval and offset values to the user equipment.

Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.

Abstract: A multiport memory emulator receives first and a second memory commands for concurrent processing of memory commands in one operation clock cycle. Data operands are stored in a memory array of bitcells that is arranged as rows and memory banks. An auxiliary memory bank provides a bitcell for physically storing an additional word for each row. The bank address portion of each of the first and second memory commands is respectively translated into a first and second physical bank address. The second physical bank address is assigned a bank address of a bank that is currently unused in response to a determination that the bank address portions are equal and the bank associated with the first bank address is designated as a currently unused bank for subsequently received memory commands in response to the determination that the bank address portions are equal. Simultaneous read and write operations are possible.

Abstract: According to one embodiment of the present invention, a method for creating bit planes from frame data for a digital mirror device is disclosed including forming data elements comprising bits of equal significance from a plurality of pixel data in the frame data, the forming including using dual index direct memory address operations.

Abstract: An ultrasound transmitter including intrinsic output zeroing is disclosed herein. A transmitter for generating ultrasound signals includes a first transmitter output driver and a first transmitter input driver. The first transmitter output driver includes an N-type device serially coupled to a P-type device. The first transmitter input driver includes an N-type device serially coupled to a P-type device. An output of the first transmitter input driver is coupled to an input of the first transmitter output driver. The first transmitter output driver drives an output of the transmitter to a first voltage and the first transmitter input driver drives the output of the transmitter to a second voltage while the first transmitter output driver is disabled.

Abstract: A DC-DC converter, having an output voltage and including at least one electronic switch; first circuitry controlling the output voltage by adjusting a switching frequency of the electronic switch, and second circuitry adjusting the switching frequency toward a target switching frequency when the switching frequency significantly deviates from the target switching frequency.

Abstract: An apparatus includes multiple first channels configured to be coupled to a first boost capacitor and multiple second channels configured to be coupled to a second boost capacitor. Each channel includes a transistor switch and a gate driver configured to drive the transistor switch. The gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in the first channels is driven using a voltage from the first boost capacitor. The gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in the second channels is driven using a voltage from the second boost capacitor. The transistor switch in each channel may include first and second transistors having their sources coupled together, and each of the channels may further include a pull-down switch configured to pull the sources of the first and second transistors to ground.

Abstract: A semiconductor device includes a semiconductor layer (2) and a dielectric stack (3) on the semiconductor layer. A plurality of etchant openings (24-1,2 . . . ) are formed through the dielectric stack (3) for passage of etchant for etching a plurality of overlapping sub-cavities (4-1,2 . . . ), respectively. The etchant is introduced through the etchant openings to etch a composite cavity (4) in the semiconductor layer by simultaneously etching the plurality of overlapping sub-cavities into the semiconductor layer.

Abstract: A method of computing a peak current density specification (jpeakspec) for an electrical conductor line of an integrated circuit (IC) resulting from conducting pulsed electrical current represented as a current waveform. An on-time (ton) is identified for the current waveform based on a current density being greater than or equal to (?) a predetermined current density level. The jpeakspec is computed for the electrical conductor line using a jpeakspec modeling equation which includes the ton for the current waveform and a thermal time constant (?) for the electrical conductor line.

Abstract: A semiconductor device includes a depletion mode GaN FET cascoded with an enhancement mode NMOS transistor. A gate of the GaN FET is electrically coupled to a source of the NMOS transistor through a gate network. The gate network controls at least one of a turn-on time and a turn-off time of the GaN FET. The gate network may be controlled by an input signal to a gate of the NMOS transistor.

Abstract: This invention is a method of memory saving in compressed video decoding. For each group of pictures the method determines whether less than the maximum number N reference frames are needed for decoding. If so, then a memory is configuring for the needed number M reference frames less than N. If not, the memory is configured for N reference frames. The group of pictures is decoding the group of pictures using the configured number of reference frames.