Abstract: A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.

Abstract: A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.

Abstract: An apparatus comprises a selected volume detector that detects a selected output volume; an analog output signal amplifier; a digital volume amplifier; a boost gain control element coupled to the selected volume detector; the analog output signal amplifier; and the digital volume amplifier; wherein the boost gain control element is configured to: keep a gain of a path of the digital volume amplifier and the analog output signal amplifier substantially constant, wherein the boost gain control element can adjust both: a) a gain of the digital volume control; and b) a gain of the analog output signal amplifier; to keep the gain of the path of the digital volume amplifier and the analog output signal substantially constant and equal to the selected output volume.

Abstract: An electronic circuit includes an electronic compass having e-compass sensors mounted on different axes and operable to supply e-compass sensor data, memory circuitry, and an electronic processor coupled to said e-compass sensors and to said memory circuitry, said electronic processor operable to execute an electronic ellipse-fitting procedure responsive to the e-compass sensor data to generate at least one signal related to an ellipse tilt angle, and store the at least one signal in said memory circuitry as a tilt calibration parameter for the e-compass. Processes for calibrating an e-compass, as well as electronic circuits and processes for correcting measured heading, and processes of manufacture are also disclosed.

Abstract: A method includes transporting audio/video data using at least one signal line in a cable. The method also includes concurrently transporting at least about 100 W of power for operating an audio/video device using at least one electrical conductor in the cable, the audio/video device coupled to the cable. The cable could include multiple electrical conductors, and the at least one signal line in the cable could include one or more of the electrical conductors in the cable. The data and the power can be transported using at least one common electrical conductor in the cable. The audio/video data could have a data rate of at least about 7 Gbps, and the power could be at least about 200 W of power.

Abstract: An energy harvesting system for transferring energy from an energy harvester (2) having an output impedance (Zi) to a DC-DC converter (10) includes a maximum power point tracking (MPPT) circuit (12) including a replica impedance (ZR) which is a multiple (N) of the output impedance. The MPPT circuit applies a voltage across the replica impedance that is equal to an output voltage (Vin) of the harvester to generate a feedback current (IZR) which is equal to an input current (Iin) received from the harvester, divided by the multiple (N), to provide maximum power point tracking between the harvester and the converter.

Abstract: A computing system comprising a processor having a first and second bus (the processor on a first semiconductor die mounted within a semiconductor package), a monitoring device coupled to both the first and second bus of the processor (the monitoring device on the first semiconductor die mounted within the semiconductor package), a memory coupled to the processor via the first bus (coupled to the monitoring device via a security signal, the memory on a second semiconductor die mounted within the semiconductor package), and a user interface external of the semiconductor package (the user interface coupled to the processor via the second data and instruction bus). The monitoring device checks one or both of the first and second busses to determine whether a secure mode entry sequence is delivered to the processor. The first bus and the security signal are only coupled to and accessible by devices within the semiconductor package.

Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.

Abstract: Methods and apparatus for parsing friendly and error resilient merge flag coding in video coding are provided. In some methods, in contrast to merging candidate list size dependent coding of the merge flag in the prior art, a merge flag is always encoded in the encoded bit stream for each inter-predicted prediction unit (PU) that is not encoded using skip mode. In some methods, in contrast to the prior art that allowed the merging candidate list to be empty, one or more zero motion vector merging candidates formatted according to the prediction type of the slice containing a PU are added to the merging candidate list if needed to ensure that the list is not empty and/or to ensure that the list contains a maximum number of merging candidates.

Abstract: An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, doped n-type throughout its length, and includes portions serving as gate electrodes of n-channel and p-channel MOS transistors; a plate of a metal-to-poly storage capacitor; and a plate of poly-to-active tunneling capacitors. The p-channel MOS transistor includes a buried channel region, formed by way of ion implantation, disposed between its source and drain regions. Silicide-block silicon dioxide blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit are silicide-clad.

Abstract: Architecture for VBUS pulsing in an Ultra Deep Sub Micron (UDSM) process for ensuring USB-OTG (On The Go) session request protocol, the architecture being of the type wherein at least a charging circuit is deployed, uses a diode-means connected in a forward path of the charging circuit. The architecture might include a diode-divider including nodes and connected from VBUS in said charging circuit. One embodiment uses both charging and discharging circuits comprising transistors. The charging circuit transistor might comprise a PMOS transistor and the discharging circuit transistor might comprise a NMOS transistor. The architecture might include a three resistance string of a total resistance value approximating 100K Ohms connected between said VBUS and ground, wherein the discharging circuit transistor might comprise a drain extended NMOS transistor. The charging and discharging circuit transistors have VDS and VGD of about 3.6V, whereby high VGS transistors are not needed.

Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.

Abstract: A system comprises a plurality of components, scan chain selection logic coupled to the components, and override selection logic coupled to the scan chain selection logic. The scan chain selection logic selects various of the components to be members of a scan chain under the direction of a host computer. The override selection logic detects a change in the scan chain and, as a result, blocks the entire scan chain from progressing.

Abstract: A global navigation satellite system (GNSS) includes an efficient memory sharing architecture that provides additional search capacity by, e.g., sharing a portion of GNSS receiver processor memory with a general processor. A memory management unit dynamically revectors memory accesses in accordance with the various states of the GNSS receiver processor and arranging the available memory as a shared memory bank that can be efficiently shared between the general processor and the GNSS receiver processor. An optional ancillary memory system can provide additional memory to the general processor when the GNSS receiver processor has allocated memory that the general processor would otherwise use.

Abstract: An integrated circuit having an SRAM cell includes a pair of cross-coupled inverters with first driver and load transistors connected to provide a first storage node and second driver and load transistors connected to provide a second storage node. The SRAM cell also includes first and second pass gate transistors controlled by at least one word line and respectively connected between a first bit line and the first storage node and a second bit line and the second storage node; wherein a first driver transistor threshold voltage is different than a second driver transistor threshold voltage and one of the first and second driver threshold voltages is different than a pass gate transistor threshold voltage. Alternately, a threshold voltage of the first and second driver transistors is different than a symmetrical pass gate transistor threshold voltage. Additionally, methods of manufacturing an integrated circuit having an SRAM cell are provided.

Abstract: A method for navigating using a speed sensor and a yaw rate sensor includes computing, for each of a plurality of error parameter values, a distance traveled for each of a plurality of directions of travel. The method also includes selecting the error parameter value that maximizes the distance traveled in one or more of the directions of travel, applying the selected error parameter value to data from the yaw rate sensor, and navigating using dead reckoning based on data from the speed sensor and data from the yaw rate sensor with the applied error parameter value.

Abstract: A semiconductor device (100) includes a leadframe having a chip pad (110) and a lead (111) with a first end (112) proximate to the pad and a second end (113) remote from the pad, the leadframe having a base metal (120) including copper and a stack of a plated first layer (121) of nickel in contact with the base metal and a plated second layer (122) of a noble metal in contact with the nickel layer, the second lead end free of the noble metal. Further included is a copper wire (104) having a ball bond (104a) on a semiconductor chip (101) attached to the chip pad, and a stitch bond (104b) on the proximate lead end, the stitch bond penetrating the second layer; furthermore a packaging compound (130) encapsulating the chip, the wire, and the first end of the lead, the compound leaving the second end of the lead un-encapsulated; and the unencapsulated second lead end covered with a plated third layer (123) of solder.

Abstract: A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

Abstract: Embodiments of the invention provide a method of decoding of hexagonal constellations. The decoding methods exploit the inherent structure of the hexagonal grid to eliminate/minimize the requirements for distance computations. A constellation which has unused constellation points is received. A plurality of lookup tables is used for indicating whether a particular constellation point is used. The lookup tables are indexed using the two integers u and v. An initial estimate ? and v is found. The Euclidean distance to the immediate neighbors resulting in the immediate upper and lower integers for ? and v is computed. From the distance to the nearest neighbor, the log-likelihood ratio value is computed.

Abstract: A bi-directional electrostatic discharge diode structure consumes substantially less silicon real estate and provides ultra-low capacitance by utilizing a p? epitaxial layer that touches and lies between an n+ lower epitaxial layer and an n+ upper epitaxial layer. A metal contact touches and lies over a p+ layer, which touches and lies over the n+ upper epitaxial layer.