Abstract: Integrated circuit inductors (5) are formed by interconnecting various metal layers (10) in an integrated circuit with continuous vias (200). Using continuous vias (200) improves the Q factor over existing methods for high frequency applications. The contiguous length of the continuous vias should be greater than three percent of the length of the inductor (5).
Abstract: A system and method to provide a slow start up voltage, such as that can slowly ramp up or down by cyclically coupling a pair of associated energy storage devices, such as capacitors, during a start-up phase. The cyclic coupling of the capacitors, in conjunction with causing a change in charge associated with a first of the storage devices, results in incremental changes in the energy of the second energy storage device over a plurality of cycles. The energy associated with the second storage device can be used to control output circuitry that provides a desired ramp output signal.
Abstract: A communications system including devices (10, 20) for transmitting and receiving wireless communications over licensed and unlicensed bands is disclosed. On the transmit side, a device (10) includes a plurality of message sources (8A, 8B, 8C) and a smart router (12) function executed by a processor (30) within the device. The smart router (12) function allocates each wireless transmission, or components of a multicomponent wireless transmission, over a licensed wireless link (LLTX) or an unlicensed wireless link (ULTX), by optimizing various factors. The allocation factors include the availability of the unlicensed and licensed channels within range of the transmitting device (10); quality of service parameters such as time delay limits, jitter limits, bandwidth requirements, and the like; cost tolerance and cost per minute factors; power consumption expectations; and a combination of these and other factors. Transmission of the wireless message over the selected wireless links is then carried out.
Type:
Grant
Filed:
April 15, 2003
Date of Patent:
July 15, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Matthew B. Shoemake, Carl M. Panasik, Jie Liang
Abstract: A hardware control loop (19) derives an AGC setting for a communication receiver based on signal strength information (16), without incurring program execution delay of a baseband processor.
Abstract: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bidirectional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of operation. The voltage translator includes edge-rate accelerators to detect signal transitions and includes configurable resistors to provide a direct current (DC) drive current and a DC bias to hold desired voltage levels. The voltage translator is operable in the open-drain mode to detect a presence of an electronic device, and is operable in the push-pull mode upon the detection of the electronic device.
Abstract: A system for, and method of, entropy coding. In one embodiment, the system includes: (1) a memory configured to contained initialized accumulated statistics coding variable values and (2) a processor configured to employ the initialized accumulated statistics coding variable values to context-adaptive encode multiple symbols until an accumulated statistics update condition occurs and updating and store the accumulated statistics coding variable values in the memory only upon occurrence of the accumulated statistics update condition.
Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.
Abstract: A method for reducing the number of channels that are scanned during a handoff situation for a wireless endpoint station in a wireless local area network (WLAN), such as an IEEE 802.11 network, by tracking past user movements within the WLAN. A suitable sequence of channels to be scanned is generated so that reduce the number of handoffs are reduced and the average time during a handoff is reduced. To reduce handoffs and handoff latencies, the principle of locality (user movement patterns tend to be repetitive) is used. By tracking the past handoffs, future handoffs are predicted.
Type:
Grant
Filed:
September 28, 2004
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Praphul Chandra, Manoj Sindhwani, David Lide
Abstract: A quantization circuit includes a plurality of resistors, a plurality of tap points, and a plurality of coarse comparators. Each coarse comparator has a first input coupled to an input voltage and a second input coupled to a corresponding coarse tap point voltage. Each coarse comparator operates during a first phase to produce a “1” only if the input voltage exceeds the corresponding coarse tap point voltage. A plurality of fine comparators each have a first input coupled to the input voltage, and each fine comparator operates during a second phase to produce a fine output level indicative of whether the input voltage exceeds a corresponding tap point voltage of a group of tap points located immediately below the tap point connected to the highest coarse comparator producing a “1”.
Abstract: The present invention provides a method of forming a metal seed layer 100. The method includes physical vapor deposition of seed metal 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also includes a RF plasma etch of the seed metal 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the seed metal 200.
Abstract: A method forms a semiconductor device comprising isolation structures that selectively induce strain into active regions of NMOS and PMOS devices. Form a hard mask layer over a semiconductor body. A resist layer is formed on the hard mask layer that exposes and defines isolation regions. The hard mask layer is patterned and trench regions are formed using the hard mask layer as a mask. An oxide trench liner that induces compressive strain into active regions of the PMOS region is formed within trench regions of the PMOS region. A nitride trench liner that induces tensile strain into active regions of the NMOS region is formed within the NMOS trench regions.
Type:
Grant
Filed:
June 29, 2005
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Ajith Varghese, Narendra Singh Mehta, Jonathan McAulay Holt
Abstract: Performance matching devices in SOI are improved by thermally isolating matched devices within a continuous body of active material. Matched devices are isolated by an insulating wall of silicon dioxide (which surrounds the devices) and the oxide layer beneath, and are arranged to minimize effects from external thermal sources.
Abstract: A technique for checking a layout design of an integrated circuit is disclosed. The technique has application to converting the design of a circuit from schematic to layout form. Instances where multiple pwell isolation tanks are coupled to the same node and where one or more pwell isolation tanks are shorted to a substrate are detected. Node breakers are inserted in the layout between pwell isolation tanks coupled to the same node and between the substrate and isolated pwell tanks coupled to the substrate. The node breakers are inserted in the circuit schematic as well to satisfy a layout versus schematic comparison. Inserting the node breakers highlights circuit component groupings as well as which tanks contain certain elements, if any. This allows designers to make a conscious decision as to the location and groupings of elements in a layout design.
Type:
Grant
Filed:
March 13, 2006
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Haim Horovitz, Mark Allenspach, Peter Fleischmann
Abstract: Methods (300, 400) are described for calibrating the implantation angle of an ion implanter utilized in the manufacture of semiconductor products. One method (300) includes implanting (330) phosphorous ions into a pilot wafer held by a wafer platen held at a starting implantation angle in the ion implanter. The phosphorous implantation into a p-doped substrate of the pilot or blank wafer, for example, forms a semiconductive sheet. The method (300) then includes changing the implantation angle (340), and implanting another wafer (330) with phosphorous ions. The angle changing (340) and implanting (330) of other wafers continues in this manner until all wafers or angles are implanted (350) as desired. The phosphorous implanted wafers are then measured (360) with a four-point probe, for example, to obtain the sheet resistance of all the implanted wafers.
Type:
Grant
Filed:
December 29, 2004
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Duofeng Yue, Jeffrey Loewecke, JieJie Xu, Thomas Patrick Conroy
Abstract: System and method for maximizing a signal strength of a received signal pulse. A preferred embodiment comprises a self-adjusting correlator/integrator (for example, correlator/integrator 325) that uses no historical timing information. The self-adjusting correlator/integrator uses a plurality of simple correlators/integrators (for example, correlator/integrator 805) which are configured to process a received signal at various times surrounding the signal pulse's expected arrival. A comparator (for example, comparator 820) selects an output of the simple correlators/integrators with greatest magnitude.
Type:
Grant
Filed:
January 2, 2003
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Anuj Batra, Anand G. Dabak, Ranjit Gharpurey
Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises forming a capping layer 610 over gate structures 230 located over a microelectronics substrate 210 wherein the gate structures 230 include sidewall spacers 515 and have a doped region 525 located between them. A protective layer 710 is placed over the capping layer 610 and the doped region 525, and a portion of the protective layer 710 and capping layer 610 that are located over the gate structures are removed to expose a top surface of the gate structures 230. A remaining portion of the protective layer 710 and capping layer 610 remains over the doped region 525. With the top surface of the gate structures 230 exposed, metal is incorporated into the gate structures to form gate electrodes 230.
Type:
Grant
Filed:
August 11, 2005
Date of Patent:
July 8, 2008
Assignee:
Texas Instruments Incorporated
Inventors:
Freidoon Mehrad, Shaofeng Yu, Joe G. Tran
Abstract: The present invention provides for a memory device comprising a bulk substrate. A first lightly doped region is formed in the bulk substrate. A first active region is formed in the first lightly doped region. A second lightly doped region is formed in the bulk substrate. A second active region is formed in the second lightly doped region. A third active region is formed in the bulk substrate. An oxide layer is disposed outwardly from the bulk substrate and a floating gate layer is disposed outwardly from the oxide layer. In a particular aspect, a memory device is provided that is a single poly electrically erasable programmable read-only memory (EEPROM) with a drain or source electrode configured to remove negative charge from the gate and erase the EEPROM, without a separate erase region.
Abstract: A semiconductor device includes a fin-fuse and an SOI transistor. The SOI transistor is located on an SOI substrate and has a source region and a drain region. The fin-fuse is connected to one of the source/drain regions and has a fusible link located on the SOI substrate. The fusible link has a homogeneous dopant concentration.