Abstract: A wireless device that includes an access point (AP) scanner, a transceiver, and a controller coupled to the AP scanner and transceiver. The AP scanner is configured to scan wireless network channels utilized by one or more APs to transmit data packets, probe responses, and beacons. The transceiver is configured to transmit one or more probe requests to the one or more APs and receive one or more probe responses and beacons from the one or more APs. The controller is configured to determine a proximate geographic position of the wireless device based on signal strength of the one or more probe responses and beacons received from the one or more APs. The controller also dynamically adapts a parameter utilized in determining the proximate geographic position of the wireless device.

Abstract: A microelectromechanical device package with integral a heater and a method for packaging the microelectromechanical device are disclosed in this invention. The microelectromechanical device package comprises a first package substrate and second substrate, between which a microelectromechanical device, such as a micromirror array device is located. In order to bonding the first and second package substrates so as to package the microelectromechanical device inside, a sealing medium layer is deposited, and heated by the heater so as to bond the first and second package substrates together.

Abstract: This invention concerns multiplexing in Long Term Evolution (LTE) and Long Term Evolution-Advanced (LTE-A) in Evolved Universal Terrestrial Radio Access Network (E-UTRAN) wireless telephony. Joint processing down link coordinated multi-point reference signaling includes combining resource signal types at a user equipment, determining conflicts between resource signals of plural user equipment, puncturing resource signals of other cell upon determining conflicts between resource signals of plural user equipment and transmitting non-punctured combined resource signals from a user equipment.

Abstract: This invention relates to a control circuit for a buck power factor correction (PFC) stage. Buck PFC stages are commonly used in low cost, high efficiency power converters. These buck PFC stages are typically controlled using a very slow control loop with a crossover frequency of the order of 10 to 20 Hz. However, such a slow response is unsuitable for applications requiring overvoltage protection. The present invention overcomes the problems with the known control circuits for buck PFC stages by implementing a two stage control circuit having a fast outer loop control circuit and a slow inner loop control circuit. The fast outer loop control circuit is in operation during low load conditions and the slow inner loop control circuit is only active under load.

Abstract: PWM control circuits and soft start circuitry thereof are presented in which a source follower circuit provides an input to a pulse generator error amplifier during startup according to a lower one of an internal soft start circuit ramp signal and a voltage across and externally connected capacitor, with a current source connected to the source follower to limit the charging current supplied to the externally connected capacitor.

Abstract: An IO circuit capable of high voltage signaling in a low voltage BiCMOS process. The IO circuit includes a voltage rail generator circuit that receives a reference voltage and generates a voltage rail supply. A BJT (bi-polar junction transistor) buffer circuit is coupled to the voltage rail generator circuit and a pad. The BJT buffer circuit includes a pull-up circuit and a pull-down circuit. The pull-up circuit receives the voltage rail supply. The pull-down circuit is coupled to the pull-up circuit. The pad is coupled to the pull-up circuit and the pull-down circuit.

Abstract: An integrated circuit device that includes a plurality of multiple gate FinFETs (MuGFETs) is disclosed. Fins of different crystal orientations for PMOS and NMOS MuGFETs are formed through amorphization and crystal regrowth on a direct silicon bonded (DSB) hybrid orientation technology (HOT) substrate. PMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (110) crystal orientations. NMOS MuGFET fins are formed with channels defined by fin sidewall surfaces having (100) crystal orienations in a Manhattan layout with the sidewall channels of the different PMOS and NMOS MuGFETs aligned at 0° or 90° rotations.

Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.

Abstract: A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register has a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.

Abstract: A test circuit for measuring a gate delay as a function of stress is disclosed. The test circuit includes an oscillator, a reference gate chain, a test gate chain, and a counter. The counter measures the difference in propagation delay between the test chain and the reference chain in calibrated oscillator cycles. Differences in test gate delay as a function of applied stress may be measured within the calibration accuracy of the oscillator frequency. The use of the reference gate chain allows a simpler unipolar counter.

Abstract: An analog to digital converter receives an analog input signal. The analog input signal is converted into a digital output signal. The converting includes shaping quantization noise in response to: a signal-to-noise ratio of the analog input signal; and a power of the converter.

Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.

Abstract: A semiconductor device containing a GaN FET has an isolating gate structure outside the channel area which is operable to block current in the two-dimensional electron gas between two regions of the semiconductor device. The isolating gate structure is formed concurrently with the gate of the GaN FET, and has a same structure as the gate.

Abstract: Apparatuses and methods for suppressing power supply noise harmonics are disclosed. A method includes selecting at least one flip-flop of a plurality of data paths of an integrated circuit based on a slack associated with the at least one flip-flop. The method also includes providing at least one delay circuit at an output of at least one flip-flop. The at least one delay circuit is configured to delay the output of the at least one flip-flop by a threshold clock cycle for managing current at a positive edge of a clock input and current at a negative edge of the clock input, thereby suppressing power supply noise harmonics of the integrated circuit.

Abstract: Operating a state machine includes enabling operation of the state machine upon receiving a signal indicating a change from operation of a test access port to a scan test port. The process maintains the state machine in an IDLE 1 state while receiving a scan test port capture signal and transitions the state machine to an IDLE 2 state when receiving a scan test port shift signal. The process then transitions the state machine to a SEQUENCE 1 state, then to a SEQUENCE 2 state, and then to a SEQUENCE 3 state when receiving sequential scan test port capture signals. The state machine then transitions to an UNLOCK TAP state and then back to the IDLE 1 state when receiving sequential scan test port shift signals on the test mode select/capture select lead.

Abstract: Disclosed embodiments demonstrate batch processing methods for producing optical windows for microdevices. The windows protect the active elements of the microdevice from contaminants, while allowing light to pass into and out of the hermetically sealed microdevice package. Windows may be batch produced, reducing the cost of production, by fusing multiple metal frames to a single sheet of glass. In order to allow windows to be welded atop packages, disclosed embodiments keep a lip of metal without any glass after the metal frames are fused to the sheet of glass. Several techniques may accomplish this goal, including grinding grooves in the glass to provide a gap that prevents fusion of the glass to the metal frames along the outside edges in order to form a lip. The disclosed batch processing techniques may allow for more efficient window production, taking advantage of the economy of scale.

Abstract: A two-step thermal treatment method consists of performing ion implantation in a silicon substrate of the semiconductor device. A first thermal treatment procedure is performed on the semiconductor device. A second thermal treatment procedure is consecutively performed on the semiconductor device to reduce damage produced by the ion implantation.

Abstract: The width of a metal contact opening is formed to be smaller than the minimum feature size of a photolithographically-defined opening. The method forms the metal contact opening by first etching the fourth layer of a multilayered hard mask structure to have a number of trenches that expose the third layer of the multilayered hard mask structure. Following this, the third, second, and first layers of the multilayered hard mask structure are selectively etched to expose uncovered regions on the top surface of an isolation layer that touches and lies over a source region and a drain region. The uncovered regions on the top surface of the isolation layer are then etched to form the metal contact openings.

Abstract: A method for brightness and contrast enhancement includes computing a luminance histogram of a digital image, computing first distances from the luminance histogram to a plurality of predetermined luminance histograms, estimating first control point values for a global tone mapping curve from predetermined control point values corresponding to a subset of the predetermined luminance histograms selected based on the computed first distances, and interpolating the estimated control point values to determine the global tone mapping curve. The method may also include dividing the digital image into a plurality of image blocks, and enhancing each pixel in the digital image by computing second distances from a pixel in an image block to the centers of neighboring image blocks, and computing an enhanced pixel value based on the computed second distances, predetermined control point values corresponding to the neighboring image blocks, and the global tone mapping curve.