Patents Assigned to Texas Instruments
  • Gating WSP capture and TAP ShiftDR with TAP IR enable
    Patent number: 8918688
    Abstract: In a first embodiment a TAP 318 of IEEE standard 1149.1 is allowed to commandeer control from a WSP 202 of IEEE standard P1500 such that the P1500 architecture, normally controlled by the WSP, is rendered controllable by the TAP. In a second embodiment (1) the TAP and WSP based architectures are merged together such that the sharing of the previously described architectural elements are possible, and (2) the TAP and WSP test interfaces are merged into a single optimized test interface that is operable to perform all operations of each separate test interface.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • IC clock doubler output gated to multiplexer and output buffer
    Patent number: 8918687
    Abstract: The disclosure describes a novel method and apparatus for providing a shadow access port within a device. The shadow access port is accessed to perform operations in the device by reusing the TDI, TMS, TCK and TDO signals that are used to operate a test access port within the device. The presence and operation of the shadow access port is transparent to the presence and operation of the test access port. According to the disclosure, the shadow access port operates on the falling edge of the TCK signal while the test access port conventionally operates on the rising edge of the TCK signal.
    Type: Grant
    Filed: May 11, 2012
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • PROCESSOR WITH EXECUTION UNIT WAIT CONTROL
    Publication number: 20140372729
    Abstract: A processor includes a processor core. The processor core includes a first execution unit and a second execution unit. The first execution unit is configured to 1) execute a complex instruction that requires multiple instruction cycles to execute; 2) generate a wait signal that when asserted suspends execution of instructions by the second execution unit for at least a portion of the execution of the complex instruction; and 3) maintain information defining parameters of the wait signal generation across interruption of the complex instruction by execution of a different instruction in the first execution unit.
    Type: Application
    Filed: June 14, 2013
    Publication date: December 18, 2014
    Applicant: TEXAS INSTRUMENTS DEUTSCHLAND GMBH
    Inventors: Horst Diewald, Johann Zipperer
  • Dielectric Waveguide with Conductive Coating
    Publication number: 20140368301
    Abstract: A dielectric waveguide (DWG) has a dielectric core member that has a length L and an oblong cross section. The core member has a first dielectric constant value. A dielectric cladding surrounds the dielectric core member; the cladding has a second dielectric constant value that is lower than the first dielectric constant. A conductive shield layer surrounds a portion of the dielectric cladding.
    Type: Application
    Filed: May 22, 2014
    Publication date: December 18, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Juan Alejandro Herbsommer, Baher Haroun
  • MULTI MASTER ARBITRATION SCHEME IN A SYSTEM ON CHIP
    Publication number: 20140372648
    Abstract: A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.
    Type: Application
    Filed: June 17, 2014
    Publication date: December 18, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Saya Goud Langadi
  • ANALOG FRONT END FOR PROXIMITY SENSING OF TUNNELING CURRENT
    Publication number: 20140368944
    Abstract: A circuit includes an input that receives a current that increases as a tunneling current sensor moves closer to a media. A high gain path is operatively coupled to the input to amplify the received current as a first amplified output. The first amplified output increases until a saturation threshold is attained for the high gain path. Further increases in the received current beyond the saturation threshold are diverted from the input as an overflow current. A low gain path is operatively coupled to the input to amplify the overflow current as a second amplified output. The second amplified output increases with the overflow current as the tunneling current sensor continues to move closer to the media.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 18, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: ARUP POLLEY, Pankaj Pandey, Bryan Bloodworth
  • Calibrating a tightly-coupled GNSS/MU integration filter
    Patent number: 8914234
    Abstract: Embodiments of the invention provide methods of calibrating a blending filter based on extended Kalman filter (EKF), which optimally integrates the IMU navigation data with all other satellite measurements (tightly-coupled integration filter). In one embodiment a coordinate transformation matrix using a latest position fix is created. The state variables (for user velocity) are transformed to a local navigation coordinate. The state variables of said integration filter is estimated. A blended calibrated position fix is the output of the method.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: June Chul Roh
  • Flow control for powerline communications
    Patent number: 8913495
    Abstract: A method of powerline communications in a powerline communications (PLC) network including a first node and at least a second node. The first node transmits a data frame to the second node over a PLC channel. The second node has a data buffer for storing received information. The second node runs a flow control algorithm which determines a current congestion condition or a projected congestion condition of the data buffer based on at least one congestion parameter. The current congestion condition and projected congestion condition include nearly congested and fully congested. When the current or projected congestion condition is either nearly congested or fully congested, the second node transmits a BUSY including frame over the PLC channel to at least the first node. The first node defers transmitting of any frames to the second node for a congestion clearing wait time.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kumaran Vijayasankar, Ramanuja Vedantham, Anand G. Dabak, Tarkesh Pande, Il Han Kim
  • Fabricating a power supply converter with load inductor structured as heat sink
    Patent number: 8910369
    Abstract: A method for fabricating a power supply converter comprises a load inductor wrapped by a metal sleeve structured to transform the inductor into a heat sink positioned to deposit layers of solder paste on a sleeve surface and on the inductor leads. A metal carrier having a portion of a first thickness and portions of a greater second thickness is placed on the solder layers of the inductor. The carrier portion of first thickness is aligned with the inductor sleeve. The carrier portions of second thickness are aligned with the inductor leads. A sync and a control FET are placed side-by-side on solder layers deposited on the carrier portion of first thickness opposite the inductor sleeve. Reflowing is preformed and the solder layers are solidified. The FETs, the carrier and the inductor become integrated and the un-soldered surfaces of the FETs and the carrier portions of second thickness become coplanar.
    Type: Grant
    Filed: May 12, 2014
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Juan A Herbsommer, Osvaldo J Lopez, Jonathan A Noquil, David Jauregui, Lucian Hriscu
  • Contactor with multi-pin device contacts
    Patent number: 8912810
    Abstract: A contactor assembly for automated testing a device under test (DUT) that includes a plurality of separate electrodes including a first electrode includes a tester load board and a contactor body coupled to the tester load board. A plurality of contactor pins carried by the contactor body includes a first contactor pin and a second contactor pin that are electrically coupled to the tester load board. The tester load board is configured to couple the plurality of contactor pins to automatic test equipment (ATE) for testing the DUT. The first contactor pin and second contactor pin are positioned to both contact the first electrode. A first path to the first contactor pin and a second path to the second contactor pin are electrically shorted together by the contactor assembly to be electrically in parallel to provide redundant paths to the first electrode during automated testing of the DUT.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Stanley Hsu, Chi-Tsung Lee, Byron Harry Gibbs
  • Methods to improve bluetooth low energy performance
    Patent number: 8913748
    Abstract: An expanded sequence number is added to PDUs in a Bluetooth® low energy system. The expanded sequence number provides more accurate identification of the PDUs and allows the system to avoid delaying transmission of PDUs while retransmitting other PDUs. A PDU security sequence number may also be added to the PDUs. The security sequence number is used to create a unique nonce for use in encrypting or decrypting and authenticating the PDU. Using the security sequence number, a failed connection can be reestablished between two devices without the need of generating an encryption key. The security sequence number allows the devices to perform encryption or decryption and authentication using an existing key and a nonce generated from the security sequence number.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jin-Meng Ho, Ariton E. Xhafa, Gangadhar Burra
  • Crack deflector structure for improving semiconductor device robustness against saw-induced damage
    Patent number: 8912076
    Abstract: An integrated circuit containing a crack deflecting scribe seal which separates an interior region of the integrated circuit from a scribeline immediately outside the integrated circuit and a method of forming the same. The crack deflecting scribe seal includes continuous metal layers and continuous contacts and continuous vias between the continuous metal layers. The continuous metal layers do not extend past the continuous contacts and continuous vias. The continuous contacts and continuous vias are recessed from edges of the underlying continuous metal layers on the scribeline side of the scribe seal, providing an angled outer surface on the scribe seal which may desirably terminate crack propagation or deflect crack propagation upward to a top surface of the scribeline or the crack deflecting scribe seal.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Thomas D. Bonifield, Basab Chatterjee
  • Self-adhesive die
    Patent number: 8912637
    Abstract: A method and apparatus for enhancing the thermal performance of semiconductor packages effectively. The concept of this invention is to provide silicon nanowires on the backside of an integrated circuit die to directly attach the die to the substrate, thereby improving the interface between die and substrate, and thus enhancing thermal performance and enhancing reliability by improving adhesion.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: December 16, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Rongwei Zhang
  • LINK AGGREGATOR WITH UNIVERSAL PACKET SCRAMBLER APPARATUS AND METHOD
    Publication number: 20140362990
    Abstract: Apparatus and methods are presented for using configurable additive data scrambling or descrambling circuitry for multichannel link aggregators in which a scrambler or descrambler polynomial is specified by binary data in a programmable register, and the polynomial data is used to compute a polynomial matrix. A scrambler or descrambler pattern is computed according to the polynomial matrix, and input data is bitwise exclusive-ORed with the computed scrambler or descrambler pattern to generate scrambled or descrambled output data. The scrambling or descrambling circuitry can be reconfigured for different polynomials by reprogramming the register, with the scrambler or descrambler automatically computing an updated polynomial matrix.
    Type: Application
    Filed: April 9, 2014
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Seuk Bo Kim, T-Pinn R. Koh
  • Leading-Edge Phase-Cut Dimmer Detector
    Publication number: 20140361705
    Abstract: Circuits and methods for detecting the presence of a leading-edge phase-cut dimmer. The dimmer detector comprises an edge detector, a pulse stretcher and a filter. The edge detector detects whether an input signal has a rapidly rising edge and generates an output signal pulse if a rapidly rising edge is detected. If the edge detector outputs a signal pulse, the pulse stretcher generates a stretched pulse having a duration that is longer than the signal pulse received from the edge detector. The filter produces a dimmer detect signal that indicates whether a leading-edge phase-cut dimmer is detected. If the pulse stretcher output signal comprises at least a predetermined number of stretched pulses within a predetermined amount of time, the dimmer signal signals the presence of a leading-edge phase-cut dimmer.
    Type: Application
    Filed: May 7, 2014
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Irwin Nederbragt, Steven Barrow
  • CAN AND FLEXIBLE DATA RATE CAN NODE APPARATUS AND METHODS FOR MIXED BUS CAN FD COMMUNICATIONS
    Publication number: 20140365693
    Abstract: Controller area network (CAN) communications apparatus and methods are presented for CAN flexible data rate (CAN FD) communications in a mixed CAN network with CAN FD nodes and one or more non-FD CAN nodes in which a CAN FD node wishing to transmit CAN FD frames sends a first predefined message requesting the non-FD CAN nodes to disable their transmitters before transmitting the CAN FD frames, and thereafter sends a second predefined message or a predefined signal to return the non-FD CAN nodes to normal operation.
    Type: Application
    Filed: April 18, 2014
    Publication date: December 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Scott A. Monroe, David W. Stout, John P. Griffith
  • SYSTEM AND METHOD FOR PULSE WIDTH MODULATION
    Publication number: 20140361829
    Abstract: A circuit for use with PWM signal having first pulse and a second pulse, wherein the first pulse has a period and a first duty cycle, and the second pulse has the period and a second duty cycle. The period has clock information therein, the first duty cycle has first data information therein, and the second duty cycle has second data information therein. The circuit includes a first integrating component and a second integrating component. The first integrating component can generate a first voltage corresponding to the first duty cycle and a second voltage corresponding to the first duty cycle. The second integrating component can generate a third voltage corresponding to the second duty cycle and a fourth voltage corresponding to the second duty cycle.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumantra Seth, Utlam Kumar Patro, Jagdish Chand Goyal, 8iman Chattopadhyay
  • LIGHTING SYSTEM
    Publication number: 20140361691
    Abstract: A lighting system includes a switch configured so that when the switch is in a first state, current from a supply flows to a light emitter, and when the switch is in a second state, current from the supply flows through the switch bypassing the light emitter. A capacitor in parallel with the light emitter provides current to the light emitter sufficient to cause the light emitter to emit light when the switch is in the second state.
    Type: Application
    Filed: December 9, 2013
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Irwin Rudolph Nederbragt, Steven Michael Barrow, Yan Yin, Craig Steven Cambier
  • LED CONTROL CIRCUITS AND METHODS
    Publication number: 20140361699
    Abstract: An LED controller is disclosed herein. An embodiment of the controller includes a first input connectable to a power source and an output connectable to at least one light-emitting diode (LED). A power factor correction circuit is coupled between the first input and the output, wherein the power factor correction circuit operates in a first state when the power factor is corrected and wherein the power factor correction circuit operates in a second state when the power factor is not corrected. The power factor correction circuit is in the first state when no dimming of the LED is sensed, and the power factor correction circuit is in the second state when dimming of the LED is sensed.
    Type: Application
    Filed: November 26, 2013
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Timothy R. Sullivan
  • Receiving a pilot design and channel estimation
    Patent number: RE45299
    Abstract: A receiver in an OFDM based communication system is adapted to perform channel estimation using a received reference signal transmitted from at least one antenna The reference signal is substantially located into at least two OFDM symbols of a transmission time interval comprising of more than two OFDM symbols. A power level of said reference signal is divided into said non-consecutive OFDM symbols in said transmission time interval and adapted to use the reference signal located in a first OFDM symbol in succeeding transmission time intervals in addition to the reference symbols in a current transmission time interval and a preceding transmission time interval.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: December 23, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Aris Papasakellariou, Timothy M. Schmidl, Eko N Onggosanusi, Anand Dabak