Abstract: In a method and system for fabricating a leadframe (100), a thickness of bondable areas (150, 152 and 154) of the leadframe (100) is reduced. A plating finish (160) is applied to a surface of the leadframe (100), including the surface of the bondable areas (150, 152 and 154) to provide a smooth texture. A selective portion (102) of the surface is removed by grinding off the plating finish (160) on the selective portion (102) to provide a rough texture while substantially preserving the smooth texture on the bondable areas (150, 152 and 154). Removal of the plating finish (160) on the selective portion (102) causes the selective portion (102) to form the rough texture, compared to the smooth texture of the plating finish (160). The rough texture provides increased adhesion to a polymeric compound compared to an adhesion provided by the smooth texture. Bondability of the bondable areas (150, 152 and 154) is maintained by preserving the smooth texture of the plating finish (160).

Abstract: A bidirectional repeater and data multiplexer for serial data comprises a plurality of comparators 302, 304, 306, 308 coupled to the respective input/output (I/O) terminals of a plurality of serial data transceiver devices A1, A2, A3, A4 such as used in I2C communication. Also coupled to these I/O terminals is a plurality of active pulldowns 316, 318, 320, 322. The outputs of the comparators are coupled to N:1 Select 310 logic wherein the desired data input is selected responsive to select lines S1, S2, S3, S4. The output of the N:1 select logic is coupled to a bidirectional control circuit 210, which couples the selected data to the control terminal of an active pulldown 206 having its source coupled to a pulldown voltage Vp low enough to represent a logic “low” level but non-zero, and a drain connected to the I/O terminal of a device B.

Abstract: The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667).

Abstract: A data switching circuit (10). The data switching circuit comprises at least one input (10in) for receiving during a same time period a plurality of data streams (ICH0-ICH127). Each of the data streams comprises a plurality of like-sized data quantities. The data switching circuit further comprises a plurality of addressable memories (10x), wherein each of the plurality of addressable memories comprises a plurality of memory cells. The data switching circuit further comprises circuitry (11) for writing into each of the plurality of addressable memories a copy of a same set of data quantities provided by the data streams during a first period of time. Lastly, the data switching circuit further comprises reading circuitry (13, 14), coupled to each respective one of the plurality of addressable memories, for reading during a second period of time a number of data quantities from the respective addressable memory and outputting the read data quantities to output channels.

Abstract: A method and system for testing a device that includes both a digital and analog portion. The digital portion includes a plurality of latch devices, and the analog portion includes a plurality of memory cells and a plurality of selector devices. A selector input controls each of the plurality of selector devices, which is electrically coupled to a respective one of the memory cells, and is indirectly coupled to one of the plurality of latch devices. A load clock loads a pattern into the plurality of latch devices. A derivative of the pattern is received by the plurality of selectors and returned to the plurality of latch devices with the assertion of the selector input. A system clock loads the derivative of the pattern into the plurality of latch devices.

Abstract: In producing data processor emulation information, program counter values used by a data processor are provided in a program counter trace stream, and a synchronization marker is inserted into the program counter trace stream. Trace information indicative of a data processing operation performed by the data processor is also provided, and a program counter value that corresponds to the data processing operation is identified. In this identification, the corresponding program counter value is expressed as an offset which indicates a number of program counter values in the program counter trace stream by which the corresponding program counter value is offset from the synchronization marker in the program counter trace stream.

Abstract: A package that resists creation of particles in a package cavity. A package according to one embodiment of the present invention contains a mechanical device attached to the floor of the package substrate. Epoxy typically is used to attach the device. Electrical connections are provided by bond wires connecting bond pads on the substrate with bond pads on the device. A window is attached to the substrate to form a cavity around the device. A thin masking layer on portions of the package cavity surface prevents the surface from generating particles. The thin masking layer may be any material that resists particle generation. The masking layer on the cavity walls optionally extends out of the cavity and onto the upper surface of the package.

Abstract: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a voltage source. The digital storage element also comprises a slave transparent latch coupled to the master transparent latch, the slave transparent latch comprising dedicated functional data and scan data output ports, a slave feedback loop and a second transistor coupled to the slave feedback loop. The second transistor is coupled to the voltage source or a different voltage source. When a clock signal is in a first state, the first single transistor is activated to reset the digital storage element. When the clock signal is in a second state, the second single transistor is activated to reset the digital storage element.

Abstract: A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.

Abstract: A serial data receiver circuit includes a pair of differential input nodes, and receiver circuitry and a termination circuit coupled between the differential input nodes. The termination circuit comprises a common mode node. A common mode control circuit is connected to the common mode node, and exhibits a substantially zero output impedance. In so doing, the common mode control circuit provides a common mode voltage to the common mode node of the termination circuit that exhibits substantially ideal termination of common mode signals and negligible loading on the differential input nodes. In another aspect, selection circuitry is provided that selectively passes single-ended or differential test signals to the differential input nodes during a test mode of operation. The selection circuitry facilitates observation of signals within the receiver circuitry.

Abstract: A multiply-accumulate module (100) includes a multiply-accumulate core (120), which includes a plurality of Booth encoder cells (104a). The multiply-accumulate core (120) also includes a plurality of Booth decoder cells (110a) connected to at least one of the Booth encoder cells (104a) and a plurality of Wallace tree cells (112a) connected to at least one of the Booth decoder cells (110a). Moreover, at least one first Wallace tree cell (112a1) or at least one first Booth decoder cell (110a1), or any combination thereof, includes a first plurality of transistors, and at least one second Wallace tree cell (112a2) or at least one second Booth decoder cell (110a2), or any combination thereof, includes a second plurality of transistors. In addition, at least one critical path of the multiply-accumulate module (100) includes the at least one first cell and a width of at least one of the first plurality of transistors is greater than a width of at least one of the second plurality of transistors.

Abstract: A voltage translator circuit is disclosed herein that eliminates the need for two supply voltages to achieve voltage translation through the use of supplying a shifted voltage threshold. Effectively, this voltage translator circuit has very little supply current (Icc) after the device switches. Specifically, the voltage translator in accordance with the present invention includes a first and second inverter coupled in series between an input node and an output node. A third inverter connects between the output node and a fourth inverter. A first circuit portion that establishes the low-to-high switching point connects between the fourth inverter and the first inverter. A second circuit portion connects between the fourth and first inverter that will block the switching current from draining the voltage supply after the transition from low-to-high has occurred.

Abstract: A technique to enable accurate timing and functional verification in a negative constraint calculation (NCC) implemented event-driven logic simulators when there are negative constraints in logic elements. In one example embodiment, the technique adjusts negative timing constraints by grouping the timing constraints based on associated output terminals in a digital logic circuit. The NCC is then applied to each grouped constraint to correct for path delays and resulting timing inaccuracy during an event driven simulation.

Abstract: A method is provided for automatically improving throughput of an active channel in a communication system comprising: receiving input from one or more modules that identify and characterize impairments in the active channel; monitoring the input to track changes in the impairments; and changing channel parameters to improve throughput on the channel based on the changes in the impairments. Other systems and methods are disclosed.

Abstract: The present invention provides a method and apparatus of converting a stream of pixel data in space and time into a stream of bitplane data. In particular, the present invention converts the pixel data stream according to a predetermined output format. The apparatus of the present invention receives the pixel data in a “real-time” fashion, and dynamically performs predefined permutations so as to accomplish the predefined transpose operation. Alternatively, the pixel data are stored in a storage medium, and the apparatus of the present invention retrieves the pixel data and performs the predefined permutation to accomplish the predefined transpose operation. The methods and apparatus disclosed herein are especially useful for processing a high-speed stream of digital data in a flow-through manner and suitable for implementation in a hardware video pipeline.

Abstract: Performing approximate analysis of modules based on corresponding layout files while requiring fewer computations than performing a transistor level simulation of a design of a module or integrated circuit. One feature enables IR/voltage drop and EM (electro migration) violations to be determined. Another features improves such analysis in case of memory modules. One more feature enables determination of whether sufficient voltages will be applied to program efuses in a module containing the efuses. Yet another feature enables the signal characteristics of an output path/pin to be determined to check for any EM violations.

Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.

Abstract: A sample-and-hold (SAH) phase detector (PD) is clocked in such a way (using a reverse clocking mode) so as to avoid quantization noise increases due to folding that is generally associated with conventional charge pump based phase detectors. The PD is clocked with a clean clock (reference clock), rather than a divided clock. The SAH PD architecture additionally includes an integrated filtering function.

Abstract: This invention efficiently converts normal pixel data into bit plane data. A sequence of pack, bitwise shuffle, masking, rotate and merging operations transform tile from pixel form to bit plane form. This enables downstream algorithms to read only the data for the bit plane of interest. This greatly reduces the memory bandwidth bottleneck and opens many new optimization pathways.

Abstract: A method of manufacturing a semiconductor device is presented. In one aspect, the method comprises forming conductive and ferroelectric material layers on a semiconductor substrate. The material layers are patterned to form electrodes and a ferroelectric layer of a ferroelectric capacitor, wherein a conductive noble metal-containing polymer is generated on sidewalls of the ferroelectric capacitor. The method also comprises converting the conductive noble metal-containing polymer into a non-conducting metal oxide. Converting includes forming a water-soluble metal salt from the conductive noble metal-containing polymer and reacting the water-soluble metal salt with an acqueous acidic solution to form a metal hydroxide. Converting also includes oxidizing the metal hydroxide to form the non-conducting metal oxide.