Patents Assigned to Texas Instruments
  • Active pull-up/pull-down circuit
    Patent number: 8901968
    Abstract: A circuit includes circuit portions operating from separate power supplies which are switched sequentially. An output of a first portion powered by a power supply (A) is provided as an input to a second portion powered by another power supply (B). Power supply (A) is switched-ON a delay interval later than power supply (B). In an embodiment, the first portion also receives a control input which enables or disables response of the first portion to changes in its inputs. An active circuit is connected between the control terminal and a constant reference potential node of the circuit, and has one transistor of a current-mirror pair connected across supplies (A) and (B). The active circuit connects the control terminal to the constant reference potential node in the delay interval, but is an open circuit otherwise. Power dissipation in the circuit is thereby reduced.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Lakshmanan Balasubramanian, Ranjit Kumar Dash
  • Phase locked loop and method for operating the same
    Patent number: 8901974
    Abstract: The invention generally relates to phase locked loops (PLL), and more specifically to ultra-low bandwidth phase locked loops. The invention may be for example embodied in an integrated circuit implementing a phase locked loop or a method for operating a phase locked loop. The invention provides a PLL with a control stage that uses only two storage cells, a counter and a digital-to-analog (DAC) converter. In comparison to prior-art PLLs using storage cells the configuration of the invention's control stage reduces the chip area required for the PLL reduced. The invention further suggests PVT compensation mechanisms for a PLL and implementing a PLL that has lower peaking in its frequency response, which results in better settling response.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Puneet Sareen, Markus Dietl, Ketan Dewan, Edmond F. George
  • Use of three-dimensional top-down views for business analytics
    Patent number: 8903119
    Abstract: A method of analyzing a depth image in a digital system is provided that includes detecting a foreground object in a depth image, wherein the depth image is a top-down perspective of a scene, and performing data extraction and classification on the foreground object using depth information in the depth image.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Goksel Dedeoglu, Vinay Sharma
  • Active low pass filter
    Patent number: 8901995
    Abstract: Sallen-Key active low pass filters (LPFs) have been knows for many years; however, these LPFs generally include passive components (i.e., resistors and capacitors) and active components (i.e., amplifiers) that are within the direct signal path that can contribute to the noise at the output of the filter within the pass band. Here, an LPF (which has the same general behavior as a Sallen-Key LPF) has been provided that AC couples passive components and active components to the direct signal path so as to suppress the noise contribution in the pass band.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Adam L. Shook
  • Video presentation at fractional speed factor using time domain interpolation
    Patent number: 8903196
    Abstract: This invention involves time domain interpolation of video signals. In order to adjust the presentation speed of a video data stream, a plurality of video frames is temporarily stored in a frame buffer, and the video frame to be displayed is generated by time domain interpolation between a plurality of the stored frames.
    Type: Grant
    Filed: October 5, 2005
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Akira Osamoto, Hiroki Yamaguchi
  • Forward error correction decoder
    Patent number: 8902925
    Abstract: A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Seuk B. Kim, Douglas E. Wente
  • Cache with multiple access pipelines
    Patent number: 8904115
    Abstract: Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Abhijeet Ashok Chachad, Raguram Damodaran, Jonathan (Son) Hung Tran, Timothy David Anderson, Sanjive Agarwala
  • Unified programmable interface for real-time Ethernet
    Patent number: 8902922
    Abstract: This invention is a low level programmable logic that can communicate with Media Independent Interface (MII) (Ethernet) interface in a highly configurable manner under the control of a CPU. This invention is highly configurable for various existing and new Ethernet based communication standards, programmable in an easy to learn assembly language, low power and high performance.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Maneesh Soni, William C. Wallace
  • System for embedded microcontroller and method
    Patent number: 8903706
    Abstract: The invention is system for emulating a target application comprises a computer, and a capsular including a microcontroller, a programmable non-volatile memory, a numeric display, a transceiver for transmitting and receiving data, a real time clock and at least one input device interacting with a program run on the microcontroller. The capsular is couplable to the computer and adapted to fit in a housing. The input device is operable both when the capsular is inside the housing and when the capsular is outside the housing.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Frank Forster, Markus Pfeiffer
  • Heat sensor correction
    Patent number: 8899828
    Abstract: A heat sensor has the ability to correct for errors introduced during temperature changes of the hot junction of the thermopile for the heat sensor. For example, the effect of temperature changes at the hot junction of the heat sensor relative to the cold junction is mathematically modeled such that the effect on the temperature determination can be corrected given certain information relating to the thermopile, its electrical output, and the temperature history and current temperature of the cold junction. By accounting for these factors, a processing device can modify the temperature determination output for the heat sensor while correcting for error introduced by temperature changes at the hot junction as determined by the mathematical model.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Habib Sami Karaki
  • Real time QRS duration measurement in electrocardiogram
    Patent number: 8903479
    Abstract: ECG data may be processed in a mobile device by receiving a stream of filtered ECG data samples comprising PQRST pattern cycles. An R point of a PQRST pattern in the filtered ECG data is determined. A portion of samples is selected from the filtered ECG data surrounding the R point. QRS duration of the PQRST pattern is then determined by processing the selected portion of samples using an application program executed by the mobile device.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Vasile Zoicas
  • Unidirectional output stage with isolated feedback
    Patent number: 8901987
    Abstract: A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.
    Type: Grant
    Filed: July 11, 2013
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jim Le, Harish Venkataraman
  • Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory scheme
    Patent number: 8904260
    Abstract: The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan (Son) Hung Tran, Abhijeet Ashok Chachad, Joseph Raymond Michael Zbiciak, Krishna Chaithanya Gurram
  • Distributed user controlled multilevel block and global cache coherence with accurate completion status
    Patent number: 8904110
    Abstract: This invention permits user controlled cache coherence operations with the flexibility to do these operations on all levels of cache together or each level independently. In the case of an all level operation, the user does not have to monitor and sequence each phase of the operation. This invention also provides a way for users to track completion of these operations. This is critical for multi-core/multi-processor devices. Multiple cores may be accessing the end point and the user/application needs to be able to identify when the operation from one core is complete, before permitting other cores access that data or code.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Raguram Damodaran, Abhijeet A. Chachad
  • POSITIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    Publication number: 20140347113
    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Steven Bartling, Sudhanshu Khanna
  • SIGNAL QUALITY ESTIMATION AND CONTROL
    Publication number: 20140348328
    Abstract: Several circuits and methods implemented to perform signal quality estimation and control are disclosed. In an embodiment, a method of signal quality estimation includes generating a demodulated signal associated with a radio signal. Information associated with a quality of the demodulated signal is accessed. Further, a value of radio frequency signal-to-noise ratio (RF-SNR) for the radio signal based on the information is estimated. Estimating the value of RF-SNR facilitates in signal quality estimation of the radio signal and control of the demodulated signal.
    Type: Application
    Filed: May 22, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Pankaj Gupta, Sriram Murali, Jaiganesh Balakrishnan, Sanjay Vishwakarma
  • CMOS Process To Improve SRAM Yield
    Publication number: 20140346609
    Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.
    Type: Application
    Filed: December 8, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Shaofeng Yu, Russell Carlton McMullan, Wah Kit Loh
  • POWER AMPLIFIER CONTROL CIRCUITS
    Publication number: 20140347124
    Abstract: Circuits for reducing power consumption in power amplifier circuits are disclosed. In certain embodiments, a circuit for power control in the transmitter includes a coupling circuit, a first power amplifier circuit and a second power amplifier circuit. The coupling circuit includes a primary winding inductively associated with a first secondary winding and a second secondary winding. The coupling circuit provides a signal at output terminals of the first secondary winding and the second secondary winding in response to a signal at the primary winding. A first power amplifier circuit is coupled with output terminals of the first secondary winding, and a second power amplifier is coupled with output terminals of the second secondary winding. The first power amplifier circuit and second power amplifier circuit are configured to be enabled or disabled based on a bias voltage.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 27, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Alok Prakash Joshi, Gireesh Rajendran
  • INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
    Publication number: 20140351665
    Abstract: The disclosure describes a process and apparatus for accessing devices on a substrate. The substrate may include only full pin JTAG devices (504), only reduced pin JTAG devices (506), or a mixture of both full pin and reduced pin JTAG devices. The access is accomplished using a single interface (502) between the substrate (408) and a JTAG controller (404). The access interface may be a wired interface or a wireless interface and may be used for JTAG based device testing, debugging, programming, or other type of JTAG based operation.
    Type: Application
    Filed: August 11, 2014
    Publication date: November 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • NEGATIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH
    Publication number: 20140347114
    Abstract: In an embodiment of the invention, a flip-flop circuit contains a 2-input multiplexer, a master latch, a transfer gate and a slave latch. The scan enable control signals SE and SEN of the multiplexer determine whether data or scan data is input to the master latch. The clock signals CLK and CLKN and retention control signals RET and RETN determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals CLK and CLN, the retain control signals RET and RETN, the slave control signals SS and SSN. The signals CLK, CLKN, RET, RETN, SS and SSN determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. Control signals RET and RETN determine when data is stored in the slave latch during retention mode.
    Type: Application
    Filed: August 12, 2014
    Publication date: November 27, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Steven Bartling, Sudhanshu Khanna