Patents Assigned to Texas Instruments
  • Publication number: 20140361755
    Abstract: DC to DC converters and pulse width modulation controllers are presented with compensation circuitry to mitigate discontinuous conduction mode (DCM) undershoot and continuous conduction mode offsets in inductor current emulation information by providing compensation signals proportional to the output voltage and the converter off time (Toff) when the low side converter switch is actuated.
    Type: Application
    Filed: June 2, 2014
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Tetsuo Tateishi, Xuening Li
  • Publication number: 20140361699
    Abstract: An LED controller is disclosed herein. An embodiment of the controller includes a first input connectable to a power source and an output connectable to at least one light-emitting diode (LED). A power factor correction circuit is coupled between the first input and the output, wherein the power factor correction circuit operates in a first state when the power factor is corrected and wherein the power factor correction circuit operates in a second state when the power factor is not corrected. The power factor correction circuit is in the first state when no dimming of the LED is sensed, and the power factor correction circuit is in the second state when dimming of the LED is sensed.
    Type: Application
    Filed: November 26, 2013
    Publication date: December 11, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Timothy R. Sullivan
  • Patent number: 8907965
    Abstract: An aspect of the present invention clips a sequence of data values within a known range (defined by a set of integer values) by a ceiling value and a floor value. In an embodiment, such a feature is obtained by first storing in each of a sequence of memory locations a respective value corresponding to each integer value, with a stored value in a memory location equaling the floor value if the memory location corresponds to an integer having a value less than the floor value, equaling the ceiling value if the memory location corresponds to an integer having a value greater than the ceiling value, and equaling the value of the corresponding integer otherwise. When a sequence of data values are thereafter received for clipping, the clipped value for each data value is obtained by merely retrieving a corresponding stored value from the corresponding location.
    Type: Grant
    Filed: April 15, 2009
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Parag Chaurasia
  • Patent number: 8907446
    Abstract: An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Scott R. Summerfelt, Byron L. Williams, Scott K. Montgomery, James Klawinsky, Asad M. Haider
  • Patent number: 8907794
    Abstract: Various cryptographic locks for securing assets, secure containers and methods of operating a cryptographic lock. One embodiment of a cryptographic lock includes: (1) a shape memory alloy (SMA) having a first and second phase, wherein the first phase inhibits access to an asset and the second phase allows access to the asset and (2) an RFID transponder, coupled to the SMA, configured to receive an authentication signal from an RFID transceiver and, based thereon, energize the SMA to temporarily change the SMA from the first phase to the second phase.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Leonardo W. Estevez, Johnsy Varghese, Steven C. Lazar
  • Patent number: 8910003
    Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8907611
    Abstract: A method for driving a motor having a plurality of phases is provided. Initially, first, second, and third intervals for a pulse width modulation (PWM) period from first and second voltage commands are generated. The first and second voltage commands correspond to a voltage vector for the motor, and the voltage vector has an associated sector. A conversion formula is then determined for the first, second, third intervals based on the associated sector for the voltage vector. Using the conversion formula and the first, second, and third intervals, fourth, fifth, and sixth intervals are generated, and a set of PWM signals for the PWM period is generated from the fourth, fifth, and sixth intervals. The motor is then driven with the second set of PWM signals, and a current traversing the plurality of phases with a single shunt is measured.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ling Qin, Bilal Akin
  • Patent number: 8906770
    Abstract: Gate cross diffusion in a semiconductor structure is substantially reduced or eliminated by forming multiple n-type gate regions with different dopant concentrations and multiple p-type gate regions with different dopant concentrations so that the n-type gate region with the lowest dopant concentration touches the p-type gate region with the lowest dopant concentration.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 8908063
    Abstract: A time-of-flight sensor device includes analog memory to store one or more sets of charges associated with a time-of-flight image frame captured by a time-of-flight pixel array. So configured, the time-of-flight sensor device greatly reduces or eliminates the need for digital memory otherwise required to store image data prior to processing.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Werner Adam Metz
  • Patent number: 8908412
    Abstract: An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIG. 7) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (714), an access transistor (716), and a sense transistor (720). A current path of each access transistor is connected in series with a current path of each respective sense transistor. A first program data lead (706) is connected to the switch of each memory cell in a first column. A bit line (718) is connected to the current path of each access transistor in the first column. A read select lead (721) is connected to a control terminal of each access transistor in the first row. A first row select lead (700) is connected to a control terminal of the switch in each memory cell in a first row.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: December 9, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Harvey J. Stiegler, Allan T. Mitchell
  • Publication number: 20140355309
    Abstract: A selected-parameter adaptively switched power conversion system, for example, includes a counter for determining a period of an output oscillation a power supply switch, where the output oscillation starts when an output current generated by stored power of the power supply coil decays substantially to zero. An event generator for generating a switching delay event in response to the determined output oscillation period and generates a switching delay event in response to a determination of a phase of the output oscillation.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 4, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Subrahmanya Bharathi Akondy, Hrishikesh Nene
  • Publication number: 20140355502
    Abstract: A device and method for controlling radio power in a wireless sensor network. A wireless sensor device includes a wireless transceiver, a white list generator, and power control logic. The wireless transceiver is configured to transmit and receive via a wireless sensor network. The white list generator configured to identify wireless sensor nodes that communicate directly with the wireless sensor device via the wireless sensor network, to identify time slots assigned for communication between the wireless sensor device and each of the identified wireless sensor nodes, and to create and maintain a list of the identified wireless sensor nodes and corresponding time slots. The power control logic is configured to power the transceiver for reception of transmissions from each identified wireless sensor node based on the identified time slots corresponding to the identified wireless sensor node provided in the list.
    Type: Application
    Filed: May 16, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ariton E. Xhafa, Xiaolin Lu, Jianwei Zhou
  • Publication number: 20140355582
    Abstract: A BLE network includes a first piconet (A) including a first master scanner (3-1) and a first group of low-power slave/advertisers (5-1,2 . . . 5) for transmitting wireless advertisements and for establishing wireless connections with the first master/scanner. Circuitry (3,55) in the first master/scanner wirelessly scans to detect an advertisement (58,62) transmitted by a first slave/advertiser (5-1) of the first group and transmits a connection request (58,62) in response to the detecting, and transmits a schedule (60) for subsequent advertisements after an initial advertisement by the first slave/advertiser to complete synchronization of the first master/scanner with the first slave/advertiser.
    Type: Application
    Filed: August 2, 2013
    Publication date: December 4, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Sandeep Kamath, Jason P. Kriek, Gregory P. Stewart, Leonardo Estevez
  • Publication number: 20140359388
    Abstract: A scan test architecture facilitates low power testing of semiconductor circuits by selectively dividing the serial scan paths into shorter sections. Multiplexers between the sections control connecting the sections into longer or shorted paths. Select and enable signals control the operation of the scan path sections. The output of each scan path passes through a multiplexer to compare circuits on the semiconductor substrate. The compare circuits also receive expected data and mask data. The compare circuits provide a fail flag output from the semiconductor substrate.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Lee D. Whetsel
  • Publication number: 20140354475
    Abstract: A method of processing received satellite signals is provided. The method includes detecting frequency, power level, code phase and doppler frequency of a plurality of satellite signals and frequency and power level of a plurality of spurious signals. The plurality of spurious signals is ranked based on one or more ranking parameters. A first subset of the plurality of spurious signals which are ranked equal or above a threshold rank are processed through a plurality of notch filters and a second subset of the plurality of spurious signals which are ranked below the threshold rank are processed through a weeding filter.
    Type: Application
    Filed: May 30, 2013
    Publication date: December 4, 2014
    Applicant: Texas Instruments Incorporated
    Inventors: Karthik SUBBURAJ, Jawaharlal TANGUDU, Sumeer BHATARA
  • Publication number: 20140355691
    Abstract: A video hardware engine with multi-threading functionality is disclosed. The video hardware engine includes a video hardware accelerator unit and a controller. The controller is coupled to the video hardware accelerator unit. The controller operates in an encode mode and a decode mode. In the encode mode, the controller receives a plurality of frames and encode attributes associated with each frame of the plurality of frames. The encode attributes associated with a frame of the plurality of frames is processed to generate encode parameters associated with the frame. The video hardware accelerator unit is configured to process the frame based on the encode parameters to generate an output. The output of the video hardware accelerator unit is processed to generate a compressed bit-stream and an encode status. In decode mode, the controller receives a compressed bit-stream and decode attributes and generates a plurality of frames and a decode status.
    Type: Application
    Filed: June 3, 2014
    Publication date: December 4, 2014
    Applicant: Texas Instruments Incorporated
    Inventor: Mihir Narendra Mody
  • Publication number: 20140359387
    Abstract: An architecture for testing a plurality of circuits on an integrated circuit is described. The architecture includes a TAP Linking Module located between test pins on the integrated circuit and 1149.1 Test Access Ports (TAP) of the plurality of circuits to be tested. The TAP Linking Module operates in response to 1149.1 scan operations from a tester connected to the test pins to selectively switch between 1149.1 TAPs to enable test access between the tester and plurality of circuits. The TAP Linking Module's 1149.1 TAP switching operation is based upon augmenting 1149.1 instruction patterns to affix an additional bit or bits of information which is used by the TAP Linking Module for performing the TAP switching operation.
    Type: Application
    Filed: August 15, 2014
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Baher S. Haroun, Lee D. Whetsel
  • Publication number: 20140354079
    Abstract: A power delivery and control device that includes a voltage input line, a voltage output line, a control logic unit coupled to the voltage input and voltage output line to control a voltage being delivered by the voltage output line based on a programmable behavior parameter, a voltage output register accessible to the control logic unit to define the programmable behavior parameter, a control register accessible to the control logic unit to activate and deactivate the voltage output line, and a control line coupled to the control logic unit to receive commands to change content of the voltage output register.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 4, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: David Thomas Bailey, Philomena Cleopha Brady, Nakshatra Shankar Gajbhiye, Eric Warren Southard
  • Patent number: 8902930
    Abstract: Systems and methods for designing, using, and/or implementing hybrid communication networks are described. In various embodiments, these systems and methods may be applicable to power line communications (PLC). For example, one or more of the techniques disclosed herein may include methods to coordinate medium-to-low voltage (MV-LV) and low-to-low voltage (LV-LV) PLC networks when the MV-LV network operates in a frequency subband mode and the LV-LV network operates in wideband mode (i.e., hybrid communications). In some cases, MV routers and LV routers may have different profiles. For instance, MV-LV communications may be performed using MAC superframe structures, and first-level LV to lower-level LV communications may take place using a beacon mode. Lower layer LV nodes may communicate using non-beacon modes. Also, initial scanning procedures may encourage first-to-second-level LV device communications rather than MV-to-first-level LV connections.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Kumaran Vijayasankar, Ramanuja Vedantham, Anand G. Dabak, Badri N. Varadarajan, Il Han Kim, Xiaolin Lu
  • Patent number: 8901995
    Abstract: Sallen-Key active low pass filters (LPFs) have been knows for many years; however, these LPFs generally include passive components (i.e., resistors and capacitors) and active components (i.e., amplifiers) that are within the direct signal path that can contribute to the noise at the output of the filter within the pass band. Here, an LPF (which has the same general behavior as a Sallen-Key LPF) has been provided that AC couples passive components and active components to the direct signal path so as to suppress the noise contribution in the pass band.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: December 2, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Adam L. Shook