Abstract: An electronic dB-to-linear gain conversion system (10). The system comprises an input (12) for receiving a gain index signal (GI) representing a desired dB value. The desired dB value is selected from a set having an integer number S of dB values. The system also comprises a storage circuit (16) for storing an integer number V of linear gain values and circuitry for producing a linear gain signal (LG) in response to the gain index signal and to one of the V linear gain values. In the preferred embodiment, V is less than S.

Abstract: A plastic integrated circuit package often includes one or more integrated circuit elements that are sensitive to outside electromagnetic fields and also may generate electromagnetic fields that may interfere with other circuits outside of the package. The package herein has a top metal film to attenuate such electromagnetic fields, using a wire loop extending through the encapsulating compound to the metal film on top of encapsulating compound to provide electrical connection between top EMI film and end-and-ground junctions at grounds on die or on end-and-ground junctions at grounds on substrate.

Abstract: The present disclosure provides a receiver, a transmitter and methods of operating a receiver and a transmitter. In one embodiment, the receiver includes a receive portion employing transmission signals from a transmitter, having multiple transmit antennas, that is capable of transmitting at least one spatial codeword and adapting a transmission rank. The receiver also includes a feedback generator portion configured to provide a channel quality indicator that is feedback to the transmitter, wherein the channel quality indicator corresponds to at least one transmission rank.

Abstract: A dual mode decoder operable with external memory. At least some of the illustrative embodiments are integrated circuit products comprising a processor portion, a memory portion coupled to the processor portion, and a hardware demodulation portion coupled to the processor portion. The processor portion and hardware demodulation portion work together to demodulate a first digital transmission signal created utilizing a first modulation system, and the processor portion and hardware demodulation portion work together to decode a second digital transmission signal created using a second modulation system different than the first modulation system (the second digital signal having at least one time interleaved segment). The integrated circuit product couples to an external memory for purposes of time de-interleaving when an amount of memory of the memory portion is insufficient for time de-interleaving for a number of segments of the second digital transmission signal.

Abstract: The present invention provides a system for controlling performance of a switch transistor (106)—one that is implemented within a circuitry segment (100) to shut off a circuitry component (116) when that component is not in use. The switch transistor has a first terminal coupled to a first supply voltage (102), a second terminal coupled to an internal voltage rail (108), a gate coupled to an activation signal source (110), and a body coupled to a bias signal source (114). A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source when that transistor is shut off. A bias signal, sufficient to induce a negative body bias across the switch transistor, is applied by the bias signal source for a period of time following assertion of an activation signal from the activation signal source that turns the switch transistor on.

Abstract: A signal processing apparatus includes: (a) A signal treating unit for effecting signal treating functions to present a treated signal at an output. (b) A clock generator receiving a clock signal and using the clock signal for presenting an internal clock signal for use by the signal treating unit. (c) A clock simulating unit occasionally coupled with at least one of the clock signal and the clock generator provides a simulated clock signal generally similar to the internal clock signal when either of the clock signal or the internal clock signal is interrupted. (d) A control unit coupled with the signal treating unit, at least one of the clock signal input locus and the internal clock generator for selectively coupling one of the internal clock signal and the simulated clock signal for use by the signal treating unit.

Abstract: Minimized Wave-zone Buoyancy is a new approach to oil and gas platform design with superior construction and performance characteristics compared to state-of-art off-shore drilling and production platforms. Minimized Wave-zone Buoyancy platforms capitalize on low cross sectional area of the portion of the platform exposed to waves. The low cross sectional area reduces buoyancy forces that result from vertical platform movement, enabling the platform to oscillate at a low natural frequency. The low cross sectional area also minimizes the cyclical vertical forces induced by waves. Compare to current designs, application of the Minimized Wave-zone Buoyancy concept will result in a lower natural frequency of oscillation, lower overall weight of platform, or both. Minimized Wave-zone Buoyancy offers an attractive alternative with improved platform stability, fatigue considerations, lower construction and installation costs, and shorter implementation schedule.

Abstract: A plasma conditioning method of improving the adhesion between an integrated circuit chip, having active and passive surfaces, the active surface polymer-coated and having a plurality of electrical coupling members, and an insulating underfill material. The method comprises the steps of positioning a wafer having a plurality of integrated circuits, including the coupling members, in a vacuum chamber of a plasma apparatus so that the polymer-coated surface faces the plasma source. Next, a plasma is initiated; the ion mean free path is controlled so that the ions reach the wafer surface with predetermined energy. The wafer surface is then exposed to the plasma for a length of time sufficient to roughen the polymer surface, clean the polymer surface from organic contamination and improve the surface affinity to adhesion. The adhesion ability of this surface to organic underfill material is thus enhanced.

Abstract: A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.

Abstract: A system comprising a processor core adapted to execute software code and a trace logic coupled to the processor core and comprising a storage. The storage comprises at least one bit that indicates a condition and status information. The trace logic generates a trace information stream associated with the processor core as the core executes the software code. If the condition is satisfied, the trace logic adjusts a status of the trace stream in accordance with the status information.

Abstract: A method of manufacturing a semiconductor device including calibrating an ion implant process. The calibration includes forming a dielectric layer over a calibration substrate. A dopant is implanted into the dielectric layer. Charge is deposited on a surface of the dielectric layer, and voltage on the surface is measured. An electrical characteristic of the dielectric layer is determined, and a doping level of the dielectric layer is determined from the electrical characteristic. The electrical characteristic is associated with an operating set-point of the ion implant process. The calibrated ion implant process is used to implant the dopant into a semiconductor substrate.

Abstract: A microelectronic device package that includes a microelectronic device encapsulated within a packaging material. The microelectronic device package also includes a lead attached to a portion of the microelectronic device extending through the packaging material. The lead has a break portion and a non-break portion on a tip of the lead.

Abstract: The method of this invention determines the timing of an integrated circuit design. At each node, the method determines if the timing of signal propagation at that node is critical. If this timing is critical, method calculates the capacitance at said current node using a highly accurate but computationally intensive model. If this timing is not critical, the method uses a less accurate but less computationally intensive model. The method calculates a signal delay for each node from the drive strength, calculated capacitance and fan-out. This signal delay is compared to a design goal. This method achieves a better trade-off between timing determination run-time and accuracy. Timing criticality can be determined from one or more of conductor length/area, fan-out, logic depth and timing slack.

Abstract: A system and method is provided for detecting an over-current condition in a power field-effect transistor (FET). In one embodiment, an over-current detection circuit for detecting an over-current condition in a power FET comprises a current generator circuit operative to generate a reference current and a plurality of matched FETs operative to receive the reference current and provide a reference voltage, the matched FETs being matched to each other and to the power FET. The over-current detection circuit also comprises a comparator operative to measure a drain-to-source voltage of the power FET and to provide an output that indicates that the drain-to-source voltage of the power FET has exceeded the reference voltage.

Abstract: Data processor emulation information that has been collected and arranged into a plurality of first information blocks during the collection process is re-arranged into a plurality of second information blocks which differ in size from the first information blocks. A sequence of the second information blocks is output from the data processor via a plurality of terminals thereof.

Abstract: The invention solves the problem of efficiently generating pseudo noise sequences with an arbitrary offset delay. Novel and improved architectures are used, based on the matrix-vector pseudo noise generators. A first embodiment of this invention includes a plurality of serially connected transition matrix multiplication circuits producing a plurality of output state matrices. A second embodiment of this invention combines a first stage having plurality of matrix multiplication circuits connected to a first multiplexer circuit which selects an state matrix or one of the matrix products with a serial chain of matrix generator circuits including second matrix multiplication circuit and a second multiplexer selecting either a first input or the output of the second matrix multiplication circuit.

Abstract: A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.

Abstract: System and method for managing finger and path resources. A preferred embodiment comprises receiving a delay profile, processing paths from the delay profile, placing the processed paths into a plurality of sets based on path criteria, and assigning the placed processed paths to demodulating fingers. A preferred embodiment further comprises the use of historical information on paths in the placing.

Abstract: A universal interface interfaces between a variety of different data processing devices by the generation, storage, proper routing, and timed output of data signals to simulate behavior of a traditional interface device dedicated to that particular communications protocol. The interface is universal because it is easily reconfigured to interface a general purpose processor with a number of communications devices, despite contrasting interface protocols, pin configuration, and other characteristics. Initially, the controller receives identification of a peripheral device's particular communications protocol. As for its input function, the controller responds to input data signals upon input/output pads by routing the signals into memory and later downloading the signals from memory under prescribed timing.

Abstract: Methods of analyzing equivalency with respect to split and limited release lots of wafers of integrated circuits. One embodiment of the split-lot method includes: (1) dividing a set of data regarding the split lot into control and experimental subsets, (2) summarizing statistics regarding the set and the subsets to an experimental unit above a site level and (3) performing a two-way analysis of variance with respect to the statistics to determine the equivalency, using the set for one way of the analysis of variance and the subsets for another way of the analysis of variance.