Abstract: An electronic device, including a first limiter including a first transistor configured to be coupled with a first side of a channel to a first output node of a non-ideal voltage source having an inner impedance greater zero in order to limit the voltage at the first output node by drawing a current from the first output node. The second side of the channel of the first transistor is coupled to a capacitor so as to supply a current from the first output node to the capacitor, if the voltage level at the output node reaches or exceeds an upper limit.

Abstract: A dynamic computational environment may create, in response to user input, a plurality of mathematical expressions. In the dynamic computational environment, a change made to any one of the plurality of mathematical expressions will be propagated to all of the mathematical expressions, such that each of the plurality of mathematical expressions affected by the change is updated.

Abstract: An operational amplifier (10) capable of driving a capacitive load (CLOAD) and/or a resistive load (RLOAD) includes a first gain stage (2) having an output coupled to a high impedance node (3) and a second gain stage (5) having an input coupled to the first high impedance node. A gain reduction resistor (RD) and an AC coupling capacitor (CD) are coupled in series between the high impedance node and a reference voltage. A Miller feedback capacitor (CM) is coupled between an output conductor (7) of the second gain stage and the high impedance node. The output of the second gain stage may be coupled to the high impedance node by a cascode transistor (MCASCODE).

Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations.

Abstract: A video device includes a first video camera, a second video camera, a motion estimating portion and an image stabilization portion. The first video camera records a first image of a first field of view, records a second image of the first field of view, outputs a first frame of image data based on the first image and outputs a second frame of image data based on the second image. The second video camera records a third image of a second field of view, records a fourth image of the second field of view, outputs a third frame of image data based on the third image and outputs a fourth frame of image data based on the fourth image. The motion estimating portion outputs a motion signal based the fourth frame of image data. The image stabilization portion modifies the second frame of image data based on the motion signal.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: In one form of the invention, a process of sending real-time information from a sender computer (103) to a receiver computer (105) coupled to the sender computer (103) by a packet network (100) wherein packets (111,113) sometimes become lost, includes steps of directing (441) packets (111) containing the real-time information from the sender computer (103) by at least one path (119) in the packet network (100) to the receiver computer (105), and directing packets (113) containing information dependent on the real-time information from the sender computer (103) by at least one path diversity path (117) in the packet network (100) to the same receiver computer (105).

Abstract: A method for secure external access to a collaborative design system is provided that includes establishing a virtual private network (VPN) tunnel between an engagement virtual machine and an external computer system, wherein the external user provides a user id and password for authorization to establish the VPN tunnel, receiving the user id and password in a web interface of the collaborative design system and identifying the engagement virtual machine the external user is allowed to access based on the user id and password, prompting the external user to log into the engagement virtual machine, wherein the user id and password are again received from the external user, issuing a security ticket to the external user when the user logs into the engagement virtual machine, and using the security ticket to authenticate accesses initiated by the external user to engagement files stored in a file system in an intranet.

Abstract: A method for using structured light in a handheld projection device is provided that includes projecting a structured light pattern in at least one portion of a frame being projected by the handheld projection device, wherein the at least one portion of the frame is a subset of the frame, capturing an image of the projected frame, computing scene depth information based on the structured light pattern in the captured image, and using the scene depth information in processing of a subsequent frame of the video stream.

Abstract: A method of displaying surveillance video streams is provided that includes receiving surveillance video streams generated by a plurality of video cameras, and displaying a selected subset of the surveillance video streams in a summary view on at least one display device, wherein, for each surveillance video stream in the summary view, only a relevant portion of each frame in the surveillance video stream is displayed, and wherein a relevant portion is a subset of a frame for at least some of the surveillance video streams in the summary view.

Abstract: Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.

Abstract: Undesired variations in a signal are removed by initializing two boundaries comprising an upper boundary and a lower boundary to track the signal level. At least one of the upper boundary and the lower boundary is adjusted encapsulate/track the received signal between the two boundaries when the signal level is outside of the two boundaries. A value computed with reference to at least one of the boundaries is provided as a filter output. As a result, the output comprises desired variations that cross the boundaries and the undesired variations that are within the boundaries are eliminated. In one embodiment, an altimeter sensor signal is filtered such that the undesired variations due to noise and instability of the altimeter are removed and the desired variations representing the change in the altitude are detected and provided without any delay to the navigation subsystem.

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract: Embodiments of the invention use signaling mechanisms that enable dynamic reconfiguration of the UL/DL resource partitioning by user equipment (UE) in a TDD wireless communication system, such as the 3GPP TDD Long Term Evolution (TD-LTE) system. The dynamic reconfiguration of the UL/DL resource partitioning disclosed herein may also be applied to any other TDD wireless system employing dynamic reconfiguration of the TDD UL/DL configuration.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: An electronic device is provided that is adapted to generate a supply voltage at an input node from a radio frequency (RF) signal. The electronic device includes a limiter coupled to the input node for limiting a supply voltage level at the input node that is generated by the received RF signal. The limiter is configured to draw a limiter current from the input node so as to limit the supply voltage level to a maximum and a magnitude of the limiter current is used for controlling a power consumption of the electronic device.

Abstract: A system in package and a method for manufacturing the same is provided. The system in package comprises a laminate body having a substrate arranged inside a laminate body. A semiconductor die is embedded in the laminate body and the semiconductor is bonded to contact pads of the substrate by help of a sintered bonding layer, which is made from a sinter paste. Lamination of the substrate and further layers providing the laminate body and sintering of the sinter paste may be performed in a single and common curing step.

Abstract: Embodiments provide systems and methods to optimize the time when to receive transmissions from dissimilar wireless networks, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during coexistence of dissimilar wireless network technologies. A receiver comprises at least two dissimilar network technology subsystems and is able to receive transmissions from dissimilar wireless network technology subsystems during a predetermined reception window.

Abstract: The disclosed switching regulator, including a controller for a switching regulator, is adaptable to supplying, or controlling the supply of, regulated current to a load that is isolated from a source of input power by a flyback transformer, and includes: (a) detecting, after transistor SWOFF, a zero crossing ZCD corresponding to a primary side switching node voltage VSW decreasing to the input voltage Vin, which occurs after a secondary current IS is substantially zero and before the next SWON; (c) establishing a time-integral window T-I_W with a leading edge corresponding to SWOFF and a trailing edge corresponding to ZCD; and (d) modulating at least the time SWOFF relative to SWON based on the primary peak current IPP at SWOFF and the time-integral window, such that a regulated load current is supplied to the load.