Abstract: A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudorandom sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.
Abstract: The present invention provides a metallization scheme, a method for manufacturing the metallization scheme, and an integrated circuit including the metallization scheme. In one aspect, the metallization scheme (300) includes a protective layer (320) located over a substrate (310), and a conductive layer (330) located over the protective layer (320). The metallization scheme (300) further includes a stress-reducing low-modulus material (340) located between the protective layer (320) and the conductive layer (330).
Abstract: A method and system is provided for determining noise components of an analog-to-digital converter. In one aspect of the invention, a method comprises providing an input signal to a signal input and a clock input of the ADC, outputting a plurality of samples at a sampled phase on the input signal for a plurality of sampled phases, and determining a jitter noise factor value, a reference noise factor value, and a total noise spectrum based on the plurality of samples for each of the plurality of sampled phases. A least means square algorithm is performed on the plurality of jitter noise factor values, reference noise factor values, and total noise spectra to estimate at least one of a jitter noise component and a reference noise component.
Abstract: An interconnect structure a substrate, a contact pad disposed over a surface of the substrate, and an insulative mask disposed over the contact pad. The insulative mask can include an opening that is aligned over and exposes an inner portion of the contact pad. The inner portion of the contact pad includes a compliant layer and a conductive layer that is disposed over the compliant layer. The inner portion of the contact pad has sufficient flexibility to distribute mechanical stress applied to the contact pad and can mitigate damage to the interconnect structure.
Abstract: System and method for decoding received information using batched processing of independent parameters. A preferred embodiment comprises a decoder (for example, decoder 210) with a memory (for example, memory 215) that may be partitioned into a plurality of parts, one of which being a parameter partition (for example, parameter partition 217). A digital signal processor (for example, DSP 205) programs the decoder 210 with various ways that it wishes received data to be decoded and the decoder 210 can operate independent of the DSP 205, storing the results of each decoding operation in a specified location. At specified instances, the decoder 210 interrupts the DSP 205 to allow the DSP 205 to retrieve the decoding results.
Type:
Grant
Filed:
May 9, 2003
Date of Patent:
November 13, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
John G. McDonough, Glbong Jeong, Der-Chieh Koon
Abstract: A communication system includes a receiver having a variable gain module and a baseband processor. The baseband processor measures the power of the signal received and derives a variable gain control setting that is inversely proportional to the power of that signal and sends the variable gain control setting to the variable gain module. The baseband processor generates a channel quality metric that is equivalent to the normalized geometric mean of the squared magnitudes of the gain estimation, divided by the total noise-plus-interference power.
Type:
Grant
Filed:
March 10, 2003
Date of Patent:
November 13, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Kofi D. Anim-Appiah, Richard G. C. Williams, Anuj Batra
Abstract: A transport packet parser (42) includes a transport packet header decoder (50) for identifying a packet identifier (PID) and continuity counter (CC) associated with a current packet. The PID along with an enable (En) bit is input to an PID associative memory (52) in search mode to identify an address associated with the PID. The address is used to access a CC associated with a previous packet for the same PID in a random access memory (62). The previous continuity counter is used along with other header information to determine whether the current packet satisfies predetermined criteria. If so, the packet is passed to a transport packet buffer for further processing.
Abstract: A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
Abstract: A semiconductor device comprising a first multi-gate device and a second multi-gate device on a semiconductor substrate. The first multi-gate device comprising a first gate structure and the second multi-gate device comprises a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
Abstract: A system for, and method of, generating an acoustic model and a heterogeneously tied mixture (HTM) acoustic model generated by means of the system and the method. In one embodiment, the system includes: (1) a first tyer configured to employ a first tying structure to tie weighted Gaussian distributions in a first pool to a first group of phones and (2) a second tyer associated with the first tyer and configured to employ a second tying structure to tie weighted Gaussian distributions in a second pool to a second group of phones, the first tying structure differing from the second tying structure, the weighted Gaussian distributions in the first pool being mutually exclusive of the weighted Gaussian distributions in the second pool, at least a criterion distinguishing the first group of phones from the second group of phones. Within each pool, different numbers of Gaussian may be assigned to different phones.
Abstract: A method for reducing gold embrittlement in solder joints, and a copper-bearing solder according to the method, are disclosed. Embodiments of the invention comprise adding copper to non-copper based solder, such as tin-lead solder. The embodiments may further comprise using the copper-bearing solder as a solder interconnect on a gold-nickel pad.
Abstract: An on-chip decoupling capacitor (106) and method of fabrication. The decoupling capacitor (104) is integrated at the top metal interconnect level (104) and may be implemented with only one additional masking layer. The decoupling capacitor (106) is formed on a copper interconnect line (104a). An aluminum cap layer (118) provides electrical connection to the top electrode (112) of the decoupling capacitor (106).
Type:
Grant
Filed:
October 30, 2003
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Timothy A. Rost, Edmund Burke, Satyavolu S. Papa Rao
Abstract: According to one embodiment of the invention, a method for estimating the failure rate of semiconductor devices includes obtaining accelerated stress duration data for a plurality of semiconductor devices, determining which of the semiconductor devices fail, classifying the defects for the failed semiconductor devices, determining a distribution model for the accelerated stress duration data, determining a set of parameters for the distribution model, determining a relative proportion of each defect classification to the total number of defect classifications, determining temperature and voltage acceleration factors for each defect classification, identifying actual operating conditions for the semiconductor devices, comparing the actual operating conditions for the semiconductor device with the distribution model, and determining a defect ratio for the semiconductor devices at the actual operating conditions for a predetermined time period based on the comparison.
Type:
Grant
Filed:
November 3, 2004
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Thomas J. Anderson, John M. Carulli, Jr.
Abstract: Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.
Type:
Grant
Filed:
September 7, 2005
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
James Joseph Chambers, Mark Robert Visokay, Luigi Colombo, Antonio Luis Pacheco Rotondaro
Abstract: System and method for detecting symbols wherein there may be a large frequency error. A preferred embodiment includes receiving an estimated frequency error, calculating a vector based on the estimated frequency error, buffering symbols from two symbol streams, rotating the symbols from the two symbol streams using the vector, estimating a channel gain for the symbols in the second symbol stream, and applying the channel gain to the rotated symbols from the second symbol stream.
Abstract: A novel and useful fast hopping frequency synthesizer and transmitter associated therewith. The frequency synthesizer and transmitter incorporates a digitally controlled oscillator (DCO) adapted to operate open loop. Instantaneous frequency switching is achieved by changing an oscillator tuning word (OTW) to imitate the three oscillators of a UWB transmitter. In one embodiment, the DCO can change the frequency instantaneously within the 1/ƒT of the varactor devices used to construct the DCO. An all digital phase lock loop (ADPLL) is used for offline calibration prior to the start of packet transmission or reception. Any phase shift during the switching is tracked by a digital circuit in the transmitter. In a second embodiment, additional frequency accuracy is provided by use of a numerically controlled oscillator (NCO) that functions to generate a fine resolution complex exponential waveform which effectively shifts the synthesized frequency.
Type:
Grant
Filed:
May 10, 2006
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Nir Tal, Robert B. Staszewski, Ofer Friedman
Abstract: System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.
Type:
Grant
Filed:
June 13, 2005
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Martin Kithinji Kinyua, William J. Bright
Abstract: A MOSFET structure with high-k gate dielectric layer and silicon or metal gates, amorphizing treatment of the high-k gate dielectric layer as with a plasma or ion implantation.
Type:
Grant
Filed:
January 25, 2006
Date of Patent:
November 6, 2007
Assignee:
Texas Instruments Incorporated
Inventors:
Mark R. Visokay, Antonio L. P. Rotondaro, Luigi Colombo
Abstract: A method of lubricating MEMS devices using fluorosurfactants 42. Micro-machined devices, such as a digital micro-mirror device (DMD™) 940, which make repeated contact between moving parts, require lubrication in order to prevent the onset of stiction (static friction) forces significant enough to cause the parts to stick irreversibly together, causing defects. These robust and non-corrosive fluorosurfactants 42, which consists of a hydrophilic chain 40 attached to a hydrophobic fluorocarbon tail 41, are applied by nebulization and replace the more complex lubricating systems, including highly reactive PFDA lubricants stored in polymer getters, to keep the parts from sticking. This lubrication process, which does not require the use of getters, is easily applied and has been shown to provide long-life, lower-cost, operable MEMS devices.
Abstract: Contention for a shared communications medium in a communications network involves a fine balancing act between wasting much network bandwidth sitting idle or recovering from collisions and transmitting data. Contention adaptation concepts are introduced for access to a shared medium, and adaptive algorithms for contention access using probabilities and backoffs are presented.