Abstract: The present invention provides a single-electron transistor device 100. The device comprises a source 105 and drain 110 located over a substrate 115 and a quantum island 120 situated between the source and drain, to form tunnel junctions 125, 130 between the source and drain. The device further includes a fixed-gate electrode 135 located adjacent the quantum island 120. The fixed-gate electrode has a capacitance associated therewith that varies as a function of an applied voltage to the fixed-gate electrode. The present invention also includes a method of fabricating a single-electron device 300, and a transistor circuit 800 that include a single-electron device 810.

Abstract: An apparatus for handling signaling between a sending device and a receiving device includes: (a) a buffering amplifier device having at least one input locus for receiving an input signal from the receiving device and having at least one output locus for presenting an output signal for the receiving device; each respective at least one output locus presents an output signal in response to the input signal received at a respective input locus of the at least one input locus; (b) a feed forward circuit coupling each respective input locus with its respective corresponding output locus to provide a feed forward signal to the respective corresponding output locus; the feed forward signal is in phase with the input signal received at the respective input locus.

Abstract: An optical module having an integral optical waveguide with waveguide ports at each end. The optical waveguide receives an input light beam through a first waveguide port. The input light beam passes through the waveguide and is emitted from the second waveguide port, where it is reflected by the reflective surface. After being reflected by the reflective surface, the input light beam can be directed onto the surface of a DMD array, where the input light beam can be selectively reflected in a particular direction. The reflective surface may also comprise a diffractive grating, thereby enabling wavelength selective switching. In addition, the reflective surface may comprise a generally concave surface that converts a diverging input light beam into a generally collimated light beam, thereby facilitating more accurate selection and switching by the DMD array.

Abstract: A processor preferably comprises a processing core that generates memory addresses to access a main memory and on which a plurality of methods operate. Each method uses its own set of local variables. The processor also includes a cache subsystem comprising a multi-way set associative cache and a data memory that holds a contiguous block of memory defined by an address stored in a register, wherein local variables are stored in said data memory.

Abstract: Computation of sprite position and size in JSR-184 with revised modelview matrix made with column vector lengths of original modelview matrix.

Abstract: The present invention provides a system for limiting degradation of a first semiconductor structure (304) caused by an electric field (314), generated from within the semiconductor substrate (302) by high voltage on a second semiconductor structure (310). A semiconductor device (300) is adapted to reduce the effective magnitude of the field—as realized at structure 304—to some fractional component (320), or to render the angle (322)—at which the field approaches the first structure through a first substrate region (306)—acute. Certain embodiments of the present invention provide for: lateral recession of the first semiconductor structure to abut an isolation structure (312), which is disposed between the second semiconductor structure and the first substrate region; lateral recession of the first semiconductor structure from the isolation structure, so as to form a moat therebetween; and a counter-doped region (316) within the first substrate region.

Abstract: An electronic device (10). The device comprises an input (16I) for receiving successive data words, wherein each data word of the successive data words comprises a plurality of bits. The device also comprises a memory structure (12) comprising a plurality of memory word addresses, wherein each memory word address corresponds to a storage structure operable to store a data word having the plurality of bits. The device also comprises control circuitry (14, 16), operable during a non-overflow condition of the memory structure, for writing successive ones of received data words into respective successive ones of the memory word addresses. Finally, the device also comprises control circuitry (14, 16), operable during an overflow condition of the memory structure, for writing each data word in successive ones of received data words across multiple ones of the memory word addresses.

Abstract: Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and field-DCT blocks, and alternatively uses de-interlacing IDCT with respect to the row dimension plus deferred column downsampling for reference frame blocks.

Abstract: Methods and apparatus to bias a backgate of a power switch while preventing latchup are disclosed. A disclosed method of biasing a backgate of a power switch comprises: if a voltage of a first power supply rises before a voltage of a second power supply, initially biasing the backgate with a voltage based on the first power supply; and if the voltage of the first power supply rises after the voltage of the second power supply, biasing the backgate with a voltage based on the second power supply.

Abstract: An integrated circuit structure includes a first dielectric layer disposed on a semiconductor layer, a first thin film resistor disposed on the first dielectric layer, a second dielectric layer disposed on the first dielectric layer and the first thin film resistor, and a second thin film resistor disposed on the second dielectric layer. A first layer of interconnect conductors is disposed on the second dielectric layer and includes a first interconnect conductor contacting a first contact area of the first thin film resistor, a second interconnect conductor contacting a second contact area of the first thin film resistor, and a third interconnect conductor electrically contacting a first contact area of the second thin film resistor. A third dielectric layer is disposed on the second dielectric layer. A second layer of interconnect conductors is disposed on the third dielectric layer including a fourth interconnect conductor for contacting the second interconnect conductor.

Abstract: An optical, line-of-sight modem. The modem includes a micro-mirror assembly including a micro-mirror and including an actuator for providing rotational movement to the micro-mirror, the micro-mirror being controllable by predetermined control signals. The modem includes a source of electronic data signals, and a source of light having a narrow beam of light directed at the micro-mirror. Means are provided for converting the electronic data signals to optical signals modulating the beam of light. Means are also provided for controlling the micro-mirror so as to maintain the micro-mirror in a predetermined position for data communication.

Abstract: A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

Abstract: An automated test system (20) for testing a high-speed communications integrated circuit (10), such as a serializer/deserializer, is disclosed. The system (20) is able to test the parameters of receiver jitter tolerance and receiver sensitivity in a loopback connection arrangement, in which serial output terminals (SERTX) of the integrated circuit (10) are connected to serial input terminals (SERRX) of the integrated circuit (10). An attenuator (26), which in the disclosed embodiment includes programmable attenuators (30P, 30N) and a fixed attenuator (32), one of which is selected, is disposed in the loopback path. A deterministic jitter injector (28) is also in the loopback path, and may be implemented by way of variable length trace blocks (35P, 35N) on the test board (30).

Abstract: A method of run-length encoding for known block size, such as image/video compression with block transform, such as DCT, with end of block indication suppressed when the end of the block can be inferred from the prior coding symbols.

Abstract: A DC-to-DC power regulator circuit, such as a synchronous buck DC-to-DC converter circuit, having improved efficiency. A power stage is provided, having an input port for receiving a DC input voltage and having an output port for providing a regulated DC output voltage. The power stage includes a control FET transistor having a first terminal, a second terminal, and a gate, the first terminal being connected to the input port. An energy storage element has a first terminal connected to the control FET output terminal and a second terminal connected to the output port. A driven FET transistor has a first terminal connected to ground, a second terminal connected to the first terminal of the energy storage element, and a gate. A driver circuit has an input adapted to receive a control signal, and provides first driver signal to the control FET gate and a second driver output signal to the driven FET gate.

Abstract: A method of performing color space conversion and under color removal. Pixelated data is first resampled (102) to an efficient word size—typically 8-bits wide. The RGB color format data words are then subtracted from a maximum intensity to yield CMY color format data words. The minimum value of the three intensity words for each pixel is determined and used as an initial black value. A scaled version of the initial black value is then subtracted from each of the four CMYK intensity words (104). The resulting CMYK values are then limited to a range bounded by the maximum and minimum producible intensities for each color.

Abstract: A distributed intelligence conferencing system is disclosed, having a plurality of conferencing nodes to connect groups of participants to a conference. Each of the conferencing nodes provides for the connection of one or more participants to the conference. Each node includes a DSP for distributed signal processing, eliminating the need for a central processor.

Abstract: The present invention provides an image-rejecting channel estimator for use with an orthogonal frequency division multiplex (OFDM) receiver employing scattered pilot channel estimates. In one embodiment, the image-rejecting channel estimator includes an estimation interpolator configured to provide channel estimates through time interpolation and frequency interpolation employing the scattered pilot channel estimates. The image-rejecting channel estimator also includes an image-rejection formatter coupled to the estimation interpolator and configured to provide image-rejection filtering to suppress an image in an output spectrum of the channel estimates from at least one of the time interpolation and frequency interpolation.

Abstract: An integrated circuit (78) includes a memory circuit (10, 110, 210, 310, 410) having a group of bitlines (21–28, 121–128, 221–228, 321–328, 421–428), and having an array of memory cells (11–18) which are each electrically coupled to two bitlines of the group. Each bitline has alternating first (61, 63, 65) and second (62, 64, 66) portions that are respectively located in metalization layers disposed on opposite sides of an insulating layer (84). The first and second portions are electrically coupled by vias (51–54, 334, 437) which extend through the insulating layer. Along the length of each bitline, each first and second portion thereof is disposed in a metalization layer opposite from the metalization layer containing the adjacent portion of each adjacent bitline.

Abstract: A method for forming a MEMS device is disclosed, where a final release step is performed just prior to a wafer bonding step to protect the MEMS device from contamination, physical contact, or other deleterious external events. Without additional changes to the MEMS structure between release and wafer bonding and singulation, except for an optional stiction treatment, the MEMS device is best protected and overall process flow is improved. The method is applicable to the production of any MEMS device and is particularly beneficial in the making of fragile micromirrors.