Patents Assigned to Texas Instruments
  • Adaptive adjustment of backoff times in wireless network communications
    Patent number: 7209467
    Abstract: A wireless network, including a plurality of network elements such as a wireless access point (9), and computer stations (2, 4, 6), is disclosed. The wireless network operates so that each network element (2, 4, 6, 9) waits for a pseudo-randomly selected duration, after the end of a frame on the channel, before initiating transmission. One of the network elements, such as the wireless access point (9), measures the performance of the network over a measurement period (T), and adjusts a minimum value of the upper limit of the range from which the random duration is selected, according to the performance of the network over the measurement period. The times measured may be the successful transmission time (Ts), which is maximized in adjusting the minimum value, or the idle and collision times (T1, Tc), which are equated in the optimization of the minimum value.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Yonghe Liu, Matthew B. Shoemake, Jin-Meng Ho
  • Trace receiver data compression
    Patent number: 7209058
    Abstract: A method repacks variable width trace data into a different packet length previous to being stored into memory. In order to conserve bandwidth, the trace data may also be compressed during transmission by eliminating the transmission of packets that have the same value.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Reducing variation in reference voltage when the load varies dynamically
    Patent number: 7209060
    Abstract: Providing a substantially constant reference voltage to a component from a reference buffer connected by a path. The load that would be offered to the reference buffer in desired durations is estimated, and a dummy load is added to the path such that the aggregate load on the path is approximately constant. In case of the stages of an ADC, the sub-code generated by each stage during a sampling phase is used to estimate the load that would be offered, and the dummy load is added in the hold phase to keep the reference voltage constant in the hold phase, as desired.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Abhaya Kumar, Visvesvaraya A Pentakota
  • Metal-halogen physical vapor deposition for semiconductor device defect reduction
    Patent number: 7208398
    Abstract: The present invention provides a method of manufacturing a metal silicide electrode (100) for a semiconductor device (110). The method comprises depositing by physical vapor deposition, halogen atoms (120) and transition metal atoms (130) to form a halogen-containing metal layer (140) on a semiconductor substrate (150). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit (400) comprising the metal silicide electrode.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Douglas E. Mercer, Noel Russell
  • Prism for high contrast projection
    Patent number: 7207678
    Abstract: Prism elements having TIR surfaces placed in close proximity to the active area of a SLM device to separate unwanted off-state and/or flat-state light from the projection ON-light bundle. The TIR critical angle of these prisms is selected to affect either the off-state light or additionally, any portion of flat-state light reflected from the SLM. To further improve the optical performance of the system, these TIR prisms can be attached directly to the SLM package, completely eliminating the package window.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Steven M. Penn
  • Apparatus and method for trace stream identification of a pipeline flattener primary code flush following initiation of an interrupt service routine
    Patent number: 7210072
    Abstract: When a PROGRAM CODE FLUSH signal is generated in a target processor during a test procedure, a sync marker is generated in a program counter trace stream. The sync marker includes a plurality of packets, the packets identifying that the sync marker is has been generated as a result of the PROGRAM CODE FLUSH signal. The program code flush sync marker identifies the absolute program counter address at the time of the generation of the PROGRAM CODE FLUSH signal and relates the PROGRAM CODE FLUSH signal sync marker to a timing trace stream. The PROGRAM CODE FLUSH signal is generated at the transition between the program (primary) code instructions being removed from the pipeline flattener and the interrupt service routine (secondary) code instructions being removed from the pipeline flattener.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Gary L. Swoboda, Bryan Thome, Manisha Agarwala
  • Method for varying the uniformity of a dopant as it is placed in a substrate by varying the speed of the implant across the substrate
    Patent number: 7208330
    Abstract: The present invention provides a method for placing a dopant in a substrate and a method for manufacturing an integrated circuit. The method for placing a dopant in a substrate, among other steps, includes providing a substrate (340) and implanting a dopant within the substrate (340) using an implant (370), the implant (370) moving at varying speeds across the substrate (340) to provide different concentrations of the dopant within the substrate (340).
    Type: Grant
    Filed: January 12, 2005
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sean M. Collins, Jeffrey G. Loewecke, James D. Bernstein
  • PC-CONNECTIVITY FOR ON-CHIP MEMORY
    Publication number: 20070089002
    Abstract: An interface for converting a traditional scan-chain interface into one where locations in the scan-chain can be read or written to from an addressed interface is provided. The interface of the invention includes a scratch pad memory into which the values at the locations in the scan-chain are copied. Those copies in the scratch pad can be read and written to using an addressed interface and if any are changed the values held in the scratch pad are shifted out to update those in the original locations in the scan-chain.
    Type: Application
    Filed: October 2, 2006
    Publication date: April 19, 2007
    Applicant: Texas Instrument, Incorporated
    Inventor: Iain Robertson
  • High frequency transmission gate buffer
    Publication number: 20070085577
    Abstract: An apparatus for providing a signal to a transmission medium. A first switching stage is connected in series between a source voltage and a transmission medium, and a second switching stage connected in series between the transmission medium and a reference line. The first and second switching stages each comprise at least one p channel transistor in parallel with at least one n channel transistor. The first and second switching stages are preferably configured to substantially symmetrically drive the transmission medium at a frequency of at least 4 gigahertz (GHz). The stages are further preferably characterized as variable resistance stages with lower resistance at the rails as compared to the midpoint of the input signal. Additional sets of stages can be provided to facilitate multiple outputs.
    Type: Application
    Filed: October 18, 2005
    Publication date: April 19, 2007
    Applicant: Texas Instruments Incorporated
    Inventor: Stanley Goldman
  • Method for voltage feedback for current mode linear motor driver
    Patent number: 7205736
    Abstract: Methods and systems for driving a motor are disclosed. A center tap voltage and a desired center tap voltage are used to generate a voltage feedback. A power amplifier receives a reference current and the voltage feedback. The power amplifier provides a phase current to a phase of a motor. The phase current is substantially centered about the desired center tap voltage as a consequence of the voltage feedback. Thus, high-side to low-side or state to state current variations are reduced thereby reducing the occurrence of problems such as torque ripple and back EMF.
    Type: Grant
    Filed: April 2, 2003
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan R. Knight, Akihiko Miyanohara
  • Circuit for high-resolution phase detection in a digital RF processor
    Patent number: 7205924
    Abstract: A novel time-to-digital converter (TDC) used as a phase/frequency detector and charge pump replacement in an all-digital PLL within a digital radio processor. The TDC core is based on a pseudo-differential digital architecture making it insensitive to NMOS and PMOS transistor mismatches. The time conversion resolution is equal to an inverter propagation delay, e.g., 20 ps, which is the finest logic-level regenerative timing in CMOS. The TDC is self calibrating with the estimation accuracy better than 1%. The TDC circuit can also serve as a CMOS process strength estimator for analog circuits in large SoC dies. The circuit also employs power management circuitry to reduce power consumption to a very low level.
    Type: Grant
    Filed: November 15, 2005
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Sudheer K. Vemulapalli, John Wallberg, Prasant K. Vallur, Robert B. Staszewski
  • Exporting on-chip data processor trace information with variable proportions of control and data
    Patent number: 7206734
    Abstract: Emulation information including emulation control information and emulation data is exported from a data processor by arranging the emulation information into information blocks, and outputting a sequence of the information blocks from the data processor. Some of the information blocks of the sequence have relative proportions of emulation control information and emulation data that differ from the relative proportions of emulation control information and emulation data in other blocks of the sequence.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Low power bus-hold circuit
    Patent number: 7205809
    Abstract: A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a first output of the first inverter and a second input coupled to a second output of the first inverter, wherein the first and second outputs of the first inverter are separated by a resistor, and having an output coupled to the bus hold input node.
    Type: Grant
    Filed: April 7, 2005
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas V. McCaughey, Eugene B. Hinterscher
  • Fast-convergence two-stage automatic gain control (AGC)
    Patent number: 7206030
    Abstract: Disclosed are methods and systems for automatic gain control (AGC) in circuits. The disclosed methods and systems provide accurate and rapidly converging automatic gain control suited for video applications. According to disclosed preferred embodiments of the invention, a signal amplitude controlling method is responsive to gain underflow or overflow. A new fine gain control value is extrapolated and a new coarse gain control value is determined. The new fine gain and new coarse gain control values are applied to the signal to produce an output signal within a pre-selected output amplitude range.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: James Edward Nave
  • Method and circuit for reduced setting time in an amplifier
    Patent number: 7205833
    Abstract: An improved method and circuit for reduced settling time in an amplifier are provided. The amplifier comprises a composite amplifier circuit including a first amplifier configured with a second amplifier comprising an integrator circuit. The reduced settling time is facilitated through implementation of a faster path configured between an inverting input terminal of the second amplifier and an output terminal of the first amplifier for current needed by an integrator resistor due to any signal appearing at said inverting input terminal for said high-speed amplifier. The faster path can be realized through the addition of a compensation capacitor between the output terminal of the composite amplifier circuit and the inverting input terminal of the second amplifier. The compensation capacitor can comprise various values depending on any given number of design criteria.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Rodney T. Burt, Joy Y. Zhang
  • Power line communication using power factor correction circuits
    Patent number: 7205749
    Abstract: A PFC circuit modulating a power line using pulse width modulation (PWM) to drive a power MOSFET and series inductor across the power line. Since many modern electronic systems include a power factor correction circuit (PFC) that already includes a series inductor and power MOSFET, a PLC is incorporated into a controller to inject a PLC transmit signal into a control loop for the PFC circuit. This can be done using either an analog PFC controller, such as the UCC28517, the UCC2819A, or a digital PFC controller such as based on a TMS320C24xx DSP.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Mark David Hagen, Robert E. Jansen
  • High-speed, low power preamplifier write driver
    Patent number: 7206155
    Abstract: A write driver circuit (38) uses a matching resistors (R0, R1) to match the impedance of the head (32) disposed between output nodes (OUTP, OUTN). Control circuitry (Q4, Q5, Q6, Q7, R2, R4, R6 and R7) maintains the voltage at reference voltage nodes (VREFP, REFN) at essentially the same voltage as its corresponding output node. The matching resistor is disposed between the reference voltage node and the output node along with a driver (40a, 40b), which may be implemented as an AB driver. Since the voltage between the reference node and the output node is generally zero, very little current is shunted by the matching resistors, and thus, there is very little power wasted by the matching resistors. In the preferred embodiment, the output transistors of the AB drivers are driven by switched current sources (Q28 and Q29) to provide enhanced current to the bases of the output transistors on an as needed basis.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jeremy Kuehlwein, Raymond E. Barnett
  • Method for forming a silicidated contact
    Publication number: 20070080408
    Abstract: A method is described for forming an at least partially silicided contact. In one embodiment, a hardmask is deposited over a contact. A coating of sacrificial material is then provided on top of the hardmask. The sacrificial material coating is etched back until the top of the contact is exposed. The contact is then opened, the sacrificial material is removed, and a silicidation of the contact is performed.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 12, 2007
    Applicants: Interuniversitair Microlektronica Centrum (IMEC), Texas Instruments Inc.
    Inventors: Philippe Absil, Jorge Kittl
  • CCM encryption/decryption engine
    Publication number: 20070081673
    Abstract: A system 10 for processing data packets according to a CCMP protocol is provided. The system includes a software component 40 operable to form a nonce and an MD according to a CCMP protocol. The system includes a hardware component 20 operable to receive the nonce and AAD and encrypt a portion of the data packet and calculate a MIC according to the CCMP protocol.
    Type: Application
    Filed: October 7, 2005
    Publication date: April 12, 2007
    Applicant: Texas Instruments Incorporated
    Inventor: Jing-Fei Ren
  • System and Method for the Probing of a Wafer
    Publication number: 20070080705
    Abstract: According to one embodiment of the invention, a method for resuming the probing of a wafer includes identifying a data set associated with a wafer. The data set identifies at least one unprobed die supported on the surface of the wafer. The method also includes determining that the data set associated with the wafer is useable and generating a probe map of the wafer from the data set. The probe map identifies a physical position associated with each unprobed die supported on the surface of the wafer. The probe map and one or more probe commands are communicated to a probe module to drive the probe module in resuming the probe of the wafer.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 12, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Glenn Schuette, James Rousey, Curtis Miller