Abstract: A wireless communication network (10) includes a wireless transmitter having a plurality of antennas (AT11, AT12). The transmitter includes for each of a plurality of different user channels (Dn), circuitry (22n) for providing a plurality of groups of symbols in a first symbol group sequence (D1n). Each of the plurality of different user channels includes circuitry (241n) for forming a first modulated symbol group sequence for the user channel by modulating the symbols in the first symbol group sequence with a unique code that corresponds to the user channel and distinguishes the user channel from each other of the plurality of different user channels and circuitry (261) for combining the first modulated symbol group sequences for transmission by a first antenna (AT11). Each of the plurality of different user channels includes circuitry (22n) for forming a second symbol group sequence (D2n) by time reversing symbols in at least some of the groups of symbols.

Abstract: The present invention provides a method for manufacturing semiconductor devices, a method for manufacturing an integrated circuit, and a method for improving a drive current for semiconductor devices on a wafer-by-wafer basis. The method for manufacturing semiconductor devices, among other elements, includes patterning gate structures on a substrate (220), each of the gate structures having a profile associated therewith, and obtaining information representative of the profiles of the gate structures (240). In accordance with the present invention the information may then be fed forward to alter a manufacturing parameter associated with a drive current of the semiconductor devices (250).

Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: System and method for correlation testing of SLMs using stroboscopic methods. A preferred embodiment comprises providing a test pattern to the SLM, configuring a pulsed light source to emit a short duration light pulse at a specified time, instructing the SLM to display the test pattern, emitting the short duration light pulse at the specified time, computing a correlation image based upon light reflected by the SLM, and determining the SLM's performance based upon the correlation image. The pulse of light permits the testing of dynamic and static characteristics of the SLM, while the use of optical computational units in the computation of the correlation image greatly reduces computational requirements and testing time.

Abstract: Thick film bond surfaces (8) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality kit (16) having raised bosses (24) engages with and compresses the bond surfaces, resulting in a flatter, wider bond surface having improved reflectivity. The personality kit (16) is fit within a clamp (30) that can be used as a stand-alone unit or integrated into an existing machine, such as a wire bonder (46).

Abstract: A PLL circuit, having a control loop for an input to a VCO including first and second charge pumps eash having an output coupled to the input of the VCO; an RC network having a first resistance and a capacitance and being and RC network coupled to the output of the first charge pump. A second resistance coupled between the output of the first charge pump and the input to the VCO, the valve of the capacitance C being reduced by a factor X, where V VCO = x C ? ? I CP2 ? t + I CP2 ? R2 VVCO=VCO input voltage Icp2 is the current output by the second charge pump R2=second resistance C?=new capacitance value=C*X C=original capacitance value.

Abstract: A quantizer employs a scaled integral inverse ratio division for quantization of an input T by a quantization step Q. The quantizer forms an integral approximation q of 2r/Q by either trunc(2r/Q) or round(2r/Q). A multiplier multiplies the absolute value of T by the q. An adjustment factor is added alternatively to the absolute value of T prior to multiplication or to the product after multiplication. This adjustment factor minimizes errors near transition points in the quantization. This invention is applicable to both trunc(T/Q) and round(T/Q).

Abstract: A microstructure and the method for making the same are disclosed herein. The microstructure has structural members, at least one of which comprises an intermetallic compound. In making such a microstructure, a sacrificial material is employed. After completion of forming the structural layers, the sacrificial material is removed by a spontaneous vapor phase chemical etchant.

Abstract: This invention corrects chrominance misalignment that occurs during chrominance down-sampling and up-sampling. The invention extracts a binary index from the corresponding luminance signal. The binary index enables generation of a filter window. On down-sampling the filter window is applied to a block of source chrominance pixels which are filtered or not based upon the binary index. On up-sampling the binary index of the filter window for the target chrominance pixels determines which are filtered or not.

Abstract: A biasing scheme is disclosed that helps reduce current noise in an associated device, such as, for example, a magneto-resistive device. The biasing scheme provides for setting a resistance path in a preamplifier, which is operative to energize the associated device, based on a biasing current that is to be used with associated device. Alternatively or additionally, the resistance path can be set based on a resistance of the associated device. As a result of setting the resistance path in this manner, noise through the associated device can be mitigated during its energization.

Abstract: A HDD write driver circuit (10) having a boost current overshoot programmed by a plurality of pull-up devices (MP35, MP36, MP39, MP45). The pull-up strength of an inverter (20) is adjustably selected by programming pull-up PMOS devices, and less power is dropped across a resistor (R41) such that there is less boost current overshoot when an overshoot MSB is low.

Abstract: The disclosed method and apparatus enables the testing of multiple embedded memory arrays associated with multiple processor cores on a single computer chip. According to one aspect, the disclosed method and apparatus identifies certain rows and columns within each of the embedded memory arrays that need to be disabled and also identifies certain redundant rows and columns in the embedded memory array to be activated. According to another aspect, the disclosed method and apparatus generates a map indicating where each of the memory failures occurs in each embedded memory array. If the testing process determines that the embedded memory array cannot be repaired, then a signal is provided directly to an external testing device indicating that the embedded memory array is non-repairable.

Abstract: The present invention relates to a hard disk drive system having overvoltage protection circuits for various types of overvoltage conditions. For example, the system comprises one or more hard disk drive integrated circuit chips residing on a board and a hard disk drive power plug receptacle residing on the board having two different value power supply ports associated therewith. The receptacle is operable to receive a power plug therein, wherein when the power plug is inserted therein in a proper orientation the two different value voltages are properly supplied to the one or more hard disk drive integrated circuit chips, and wherein when the power plug is inserted therein in an improper orientation the two different value voltages are switched with respect to their intended values. The system comprises a reverse power plug orientation protection circuit coupled between the hard disk drive power plug receptacle and at least one of the one or more hard disk drive integrated circuit chips.

Abstract: Methods and systems are provided for dynamically managing the power consumption of a digital system. These methods and systems broadly provide for varying the frequency and voltage of one or more clocks of a digital system upon request by an entity of the digital system. An entity may request that the frequency of a clock of the processor of the digital system be changed. After the frequency is changed, the voltage point of the voltage regulator of the digital system is automatically changed to the lowest voltage point required for the new frequency if there is a single clock on the processor. If the processor is comprised of multiple processing cores with associated clocks, the frequency is changed to the lowest voltage point required by all frequencies of all clocks.

Abstract: A PCI Express to PCI bridge enables upstream and downstream isochronous data transfer by modifying the PCI bus arbiter so that the PCI device on the PCI bus is treated as a virtual port for the bridge. Data from the PCI device is assigned via a port arbitration table to sufficient bandwidth so that the data from the PCI device can be transferred upstream isochronously. The bridge also handles downstream isochronous data transfer.

Abstract: A substrate (300) for a package of high frequency semiconductor devices comprising a planar insulating substrate having a plurality of parallel, planar metal layers (301a, 301b, etc.) embedded in the insulator. The substrate further has at least one pair of parallel, metal-filled vias (302 and 303) traversing the substrate; the vias have a diameter and a distance from each other of at least this diameter. The metal in each via has a sheet-like extension (321a, 321b, etc.) in each of selected planes of said metal layers, resulting in an increased via-to-via capacitance so that the reflection of a high frequency signal is less than 10%.

Abstract: A method of fabricating an electrically conductive via and an SOI structure and the structure. A substrate and a device wafer are provided and an electrically insulating layer having an outer face is formed on one of the substrate or device wafer. The insulating layer has an electrical interconnect structure therein, a portion extending to the outer face of the insulating structure. The outer surface of the insulating layer is bonded to the other of the substrate or device wafer. A portion of the insulating layer can be disposed between the interconnect structure and at least one of the substrate or device wafer with ultimate interconnection made by applying a voltage across the portion of the insulating layer sufficient to break down the portion of the insulating layer while maintaining the integrity of the remainder of the SOI structure. At least one of the device layer and substrate includes a bond region with the interconnect structure contacting the bond region.

Abstract: A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by combining HF at 49% concentration with H2O2 at 29%–30% concentration in deionized water.

Abstract: Plural scan test paths (401) are provided to reduce power consumed during testing such as combinational logic (101). A state machine (408) operates according to plural shift states (500) to control each scan path in capturing data from response outputs of the combinational logic and then shifting one bit at a time to reduce the capacitive and constant state power consumed by shifting the scan paths.

Abstract: Functional circuits and cores of circuits are tested on integrated circuits using scan paths. Using parallel scan distributor and collector circuits for these scan paths improves test access of circuits and cores embedded within ICs and reduces the IC's power consumption during scan testing. A controller for the distributor and collector circuits includes a test control register, a test control state machine and a multiplexer. These test circuits can be connected in a hierarchy or in parallel. A conventional test access port or TAP can be modified to work with the disclosed test circuits.