Abstract: In accordance with the present electronic design automation (EDA) for integrated circuits invention prior to synthesis, dummy elements are added to the library and an internal scan clock pin with no connections is provided. Then the design is synthesized, scan insertion is performed (defining scan chains, inserting chains), and the scan clock is connected to all flip-flops SCLK pins. Finally, the dummy elements are replaced with real gates and clock tree insertion is performed after placing the cell in a layout.

Abstract: This invention is used in a real time system that includes a host processor, interface hardware and an external device controlled by the interface hardware. To maintain system real-time performance, handshake protocol between the external device and the interface hardware is automatic during command execution. This invention moves control of the external device to the host processor if a command doesn't finish before a host processor specified time limit. If command execution exceeds the time limit, the host processor controls the handshake protocols directly and sequentially. This prevents system breakdown caused by trouble at the external device.

Abstract: A shallow trench isolation (STI) test pattern comprising a plurality of test structures. Each of the test structures comprise at least two lines comprising a predefined line length, line width, and gap between the lines. At least one of the line length, line width and gap are different between each of the plurality of the test structures.

Abstract: The present invention provides a metal oxide semiconductor (MOS) device, a method of manufacture therefore, and an integrated circuit including the same. The metal oxide semiconductor (MOS) device (100), without limitation, may include a first accumulation mode transistor device (120, 160) located over or in a substrate (110), as well as a second enhancement mode transistor (140, 180) device located over or in the substrate (110).

Abstract: A programmable gain low noise amplifier includes a tail current transistor (Q3) having a source coupled to a first reference voltage (VDD) and a drain coupled to a tail current conductor (18) and, in a differential input embodiment, a plurality of pairs (Q4,5, Q7,8, Q10,11, Q13,14) of differentially coupled input transistors. Each pair includes a first input transistor having a gate coupled to a first input conductor (19A) and a drain coupled to a first output conductor (26A) and a second input transistor having a gate coupled to a second input conductor (19B), a source coupled to a source of the first transistor, and a drain coupled to a second output conductor (26B). The sources of the first and second input transistors of some or all of the pairs are selectively coupled to the tail current conductor (18) in it response to corresponding gain control signals (B1,2,3).

Abstract: A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator.

Abstract: A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memories, while all other circuitry can be either placed in a low power data retention mode, or completely powered off. There is no need to rescan the repair data from the E-fuse farm after one or more memories are powered back up. This provides dynamic power savings since there is no longer any need to idle the system to reload repair data. Since the E-fuse farm can be powered down after initial system power-up and repair data is loaded into the memories, there is also a significant leakage power savings.

Abstract: This invention is a method of complex cache memory analysis and synthesis. This invention proceeds in the normal fashion of writing a program and simulating it, but makes use of a closed loop design approach to completing the analysis-synthesis process. A program behavior analysis tool PBAT is integrated as part of an otherwise conventional program development tool. The PBAT offers a single environment where code development, simulator trace capture, and cache analysis take place. The cache analysis tool of PBAT is designed to match the current cache design of the processor and to identify any weakness in the current design or special features that need to be added. Code adjustments are passed back to the assembler and linker and in successive simulations using the integrated PBAT tool resulting in code that better fits a specific cache design.

Abstract: A semiconductor package comprising a die adjacent a substrate, a supporting plate adjacent the die, and a conducting plate abutting the supporting plate and electrically coupled to a metal apparatus adjacent the substrate and the die using a plurality of bond wires. The metal apparatus supplies power to the conducting plate.

Abstract: An inductor based DC-DC converter of the present invention employs two power switches such that only a fraction of inductor current flows through sensing circuitry. The sensing circuitry itself is comprised of sense transistors instead of resistors in order to further reduce power dissipation and temperature variations. The sensing circuitry includes a differential power supply that modifies a sense current employed as feedback to one of its inputs. The sense transistors are selected and configured such that the sense current is a relatively constant fraction of the inductor current of the converter.

Abstract: A method of operating a class D amplifier output stage that compensates for nonlinearity introduced by a residual load current during the dead time in the switching of the output stage. The amplifier output stage includes an input, a gate driver circuit, two output transistors, an output, and a current sensing circuit. The transistors are serially connected between the terminals of a power supply. A residual load current flows through the transistors when they are switched off. The gate driver circuit increases or decreases the duty cycles of signals driving the transistors based on the direction of the residual load current flowing through the transistors, thereby causing the duty cycle of the amplifier output to remain substantially constant and equal to the duty cycle of the amplifier input.

Abstract: A receiver 100 is provided. The receiver 100 comprises an in-phase analog-to-digital converter 112 operable to detect a saturation condition of the in-phase analog-to-digital converter 112 and to adjust the amplitude of a in-phase signal processed by the in-phase analog-to-digital converter 112 to remove the in-phase analog-to-digital converter 112 from the saturation condition and a in-phase digital filter 114 operable to adjust a gain applied to a digital input to the in-phase digital filter 114 from the in-phase analog-to-digital converter 112, the adjustment of the gain substantially inversely proportional to the adjustment of the amplitude of the in-phase signal processed by the in-phase analog-to-digital converter 112. In an embodiment, the receiver 100 also comprises a quadrature path that is substantially similar to the in-phase path, and the in-phase path and the quadrature path comprise a direct conversion receiver.

Abstract: The spatial light modulator of the present invention comprises an array of micromirrors, each of which has a reflective deflectable mirror plate. A set of posts are provided for holding the mirror plates on a substrate, but not all micromirrors of the micromirror array have posts.

Abstract: A method is provided to automatically identify noise events in a channel of a communication system comprising the steps of: receiving an input signal from the channel; determining the mean energy of the input signal; determining the recent energy of the input signal; identifying a beginning of the noise event when the recent energy is greater than the product of the mean energy and a predefined first threshold; identifying an end of a noise event when the recent energy is less that the product of the mean energy and a predefined second threshold; and providing for output the beginning of the noise event and the end of the noise event. Other systems and methods are disclosed.

Abstract: The present invention provides a photoresist removal process and a method for manufacturing an interconnect using the same. One embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, and removing the photoresist layer using a plasma which incorporates a gas which includes hydrogen or deuterium and a small amount of oxygen less than about 20 volume percent of the gas. Another embodiment of the photoresist removal process includes, among other steps, providing a low dielectric constant (k) substrate having a photoresist layer located thereover, removing a bulk portion of the photoresist layer using a plasma which incorporates a gas which includes hydrogen or deuterium, and removing a small portion of the photoresist layer using a plasma which incorporates a gas which includes oxygen, wherein the order of the two removing steps is interchangeable.

Abstract: An information carrier medium containing debugging software that, when executed by a processor, causes the processor to generate an event signal and an event code and provide the event signal and the event code to an event detection logic coupled to the processor. The event detection logic is adapted to generate a plurality of events, where a number of events generated corresponds to the event code.

Abstract: In a method and system for testing a device, a tester provides a first plurality of test signals to the device. A test module includes a plurality of logic circuits operable to concurrently execute a plurality of test programs. The concurrent execution of the plurality of test programs generates a second plurality of test signals. The plurality of logic circuits control a plurality of switches in which each one of the plurality of switches is selectively controlled to provide one of the first plurality of test signals and the second plurality of test signals to/from the device.

Abstract: An emulator for emulating operations of data processing circuitry normally connected to and cooperable with a peripheral circuit includes serial scanning circuitry connectable to the peripheral circuit. The serial scanning circuitry provides to and receives from the peripheral circuit signals which would normally be provided and received by the data processing circuitry. The serial scanning circuitry is connectable to an emulation controller for transferring serial data between the emulation controller and the emulator. The serial scanning circuitry includes a first state machine having plural states controlling the transfer of serial data. The emulator further includes control circuitry connected to the serial scanning circuitry and connectable to the emulation controller.

Abstract: A system and method for improved performance and optimization of data exchanges over a communications link is described, including a method for communicating data that includes transmitting a first control segment of a message from a first system to a second system (the first control segment including control information that selects an active communications protocol from a plurality of communications protocols); sequencing at least part of the first and second systems through a series of states that control the active communications protocol based upon the control information in the first control segment; and exchanging a data segment of the message (after the first control segment) between the first system and the second system The series of states represents inert sequences to the remaining communications protocols of the plurality of communications protocols that were not selected as active.

Abstract: The present invention provides, in one embodiment, method of forming a barrier layer 300 over a semiconductor substrate 110. The method comprises forming an opening 120 in an insulating layer 130 located over a substrate thereby uncovering an underlying copper layer 140. The method further comprises exposing the opening and the underlying copper layer to a plasma-free reducing atmosphere 200 in the presence of a thermal anneal. The also comprises depositing a barrier layer in the exposed opening and on the exposed underlying copper layer. Such methods and resulting conductive structures thereof may be advantageously used in methods to manufacture integrated circuits comprising copper interconnects.